Chapter2
Configuration Interfaces
Virtex?-5 devices have six configuration interfaces. Each configuration interface
corresponds to one or more configuration modes and bus width, shown in Table2-1. For detailed interface timing information, see DS202, Virtex-5 FPGA Data Sheet: DC and Switching Characteristic.
Table 2-1:Virtex-5 Device Configuration Modes
Configuration ModeMaster Serial(2)Master SPI(2)Master BPI-Up(2)Master BPI-Down(2)Master SelectMAP(2)JTAG
Slave SelectMAPSlave Serial
Notes:
1.Parallel configuration mode bus is auto-detected by the configuration logic.
2.In Master configuration mode, the CCLK pin is the clock source for the Virtex-5 internal configuration logic. The Virtex-5 CCLK output pin must be free from reflections to avoid double-clocking the
internal configuration logic. Refer to the “Board Layout for Configuration Clock (CCLK)” section formore details.
M[2:0]000001010011100101110111
Bus Width
118, 168, 168, 1618, 16, 32
1
CCLK Direction
OutputOutputOutputOutputOutputInput (TCK)InputInput
Serial Configuration Interface
In serial configuration modes, the FPGA is configured by loading one configuration bit per CCLK cycle:??
In Master Serial mode, CCLK is an output.In Slave Serial mode, CCLK is an input.
Figure2-1 shows the basic Virtex-5 serial configuration interface.There are four methods of configuring an FPGA in serial mode:???
Master serial configurationSlave serial configurationSerial daisy-chain configuration
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
SelectMAP Configuration Interface
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 2:Configuration Interfaces
???
Sending a bitstream to the data pin follows the same bit-swapping rule as inSelectMAP mode. See “Parallel Bus Bit Order.”
If Flash programming is not required, FCS_B, FOE_B, and FWE_B can be tied off; thatis, DONE is connected to FCS_B, FOE_B is tied Low, and FWE_B is tied High.The CCLK outputs are not used to connect to Flash but are used to sample Flash readdata during configuration. All timings are referenced to CCLK. The CCLK pin mustnot be driven or tied High or Low.
The RS[1:0] pins are not connected as shown in Figure2-22. These output pins areonly required for MultiBoot configuration. See Chapter8, “Reconfiguration andMultiBoot.”
HSWAPEN must be connected to either disable or enable the pull-up resistors.If HSWAPEN is left unconnected or tied High, a pull-up resistor is required forFCS_B.
If HSWAPEN is tied Low, the FCB_B, FOE_B, FWE_B, and the address pins haveinternal weak pull-up resistors during configuration. After configuration, FCS_B canbe either controlled by I/O in user mode or by enabling a weak pull-up resistorthrough constraints.
To enable the active driver on DONE, the DriveDONE option in BitGen must beenabled.
“MultiBoot Bitstream Spacing,” page155 provides information on when DCI or DCMlock wait is turned on.
For daisy chaining FPGAs in BPI mode, see Figure2-12, page52.
The BPI Flash vendor data sheet should be referred to for details on the specific Flashsignal connectivity. To prevent address misalignment, close attention should be paidto the Flash family address LSB for the byte/word mode used. Not all Flash familiesuse the A0 as the address LSB.
?
???
????
Table2-9 defines the BPI configuration interface pins.
If the FPGA is subject to reprogramming or fallback during configuration from the BPI flash, then the INIT pin can be connected to the BPI reset to set the BPI into a known state.
Table 2-9:
Virtex-5 Device BPI Configuration Interface Pins
Type Input
Dedicated or Dual-Purpose
010 = BPI-Up mode011 = BPI-Down mode
HSWAPEN
Input
Dedicated
Controls I/O (except Bank 0 dedicated I/Os) pull-up resistors during configuration. This pin has a built-in weak pull-up resistor.0 = Pull-up during configuration1 = 3-state during configuration
DONE
Bidirectional, Dedicated Active-High signal indicating configuration is complete: Open-Drain, 0 = FPGA not configured or Active
1 = FPGA configured
Description
Pin Name M[2:0]
Dedicated The Mode pins determine the BPI mode:
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
Byte Peripheral Interface Parallel Flash Mode
Table 2-9:Virtex-5 Device BPI Configuration Interface Pins (Continued)
Type
Dedicated or Dual-Purpose
Description
Pin Name INIT_B
Input or Dedicated Before the Mode pins are sampled, INIT_B is an input that can be held Output, Low to delay configuration. After the Mode pins are sampled, INIT_B Open-Drain is an open-drain, active-Low output indicating whether a CRC error
occurred during configuration:
0 = CRC error 1 = No CRC error
When the SEU detection function is enabled, INIT_B is optionally driven Low when a read back CRC error is detected.
PROGRAM_B Input Dedicated Active-Low asynchronous full-chip reset
CCLK Output
Dedicated Configuration clock output. CCLK does not directly connect to BPI
Flash but is used internally to generate the address and sample read data. Dual
Active-Low Flash chip select output. This output is actively driven Low during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Active-Low Flash output enable. This output is actively driven Low during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Active-Low Flash write enable. This output is actively driven High during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Address output. For I/O bank locations, see Table1-2, page17.
FCS_BOutput
FOE_B Output Dual
FWE_BOutputDual
ADDR[25:0]OutputDual
D[15:0]InputDual
Data input, sampled by the rising edge of the FPGA CCLK. For I/O bank location, see Table1-2, page17.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
FPGA可编程逻辑器件芯片XC2S1200E-4FGG320I中文规格书 - 图文
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