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FPGA可编程逻辑器件芯片EP2AGX95EF35C6N中文规格书 - 图文

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AIIGX51004-4.0

Arria II Device Handbook Volume 1: Device Interfaces and IntegrationDecember 2010

Chapter 4:DSP Blocks in ArriaII Devices

DSP Block Overview

Arria II Device Handbook Volume 1: Device Interfaces and Integration

Chapter 4:DSP Blocks in ArriaII DevicesDSP Block Overview

Table4–1 lists the number of DSP blocks in ArriaII devices.

Table4–1.Number of DSP Blocks in Arria II Devices(Note1)

High Precision Multiplier Adder Mode

Four Multiplier Adder Mode

DSP BlocksIndependent Input and Output Multiplication Operators

FamilyDevice

9×9 12×12 18×18 MultipliersMultipliersMultipliers

2323124485766567368009201,040

174234336432492552600690780

116156224288328368400460520

18 × 18 Complex5878112144164184200230260

36 × 36 18 × 36 18 × 18 MultipliersMultipliersMultipliers

5878112144164184200230260

116156224288328368400460520

2323124485766567368009201,040

EP2AGX45EP2AGX65

Arria II GX

EP2AGX95EP2AGX125EP2AGX190EP2AGX260EP2AGZ225

Arria II GZ

EP2AGZ300EP2AGZ350

Note to Table4–1:

293956728292100115130

(1)The numbers in this table represents the numbers of multipliers in their respective mode.

Each DSP block occupies four logic array blocks (LABs) in height and you can divide further into two half blocks that share some common clocks signals, but are for all common purposes identical in functionality. Figure4–1 shows the layout of each block.

Figure4–1.Overview of DSP Block Signals

Control3414472OutputDataHalf-DSP BlockInputData28814472Half-DSP BlockOutputDataFull-DSP BlockArria II Device Handbook Volume 1: Device Interfaces and Integration

Chapter 4:DSP Blocks in ArriaII Devices

Simplified DSP Operation

Simplified DSP Operation

In ArriaII devices, the fundamental building block is a pair of 18×18-bit multipliers followed by a first-stage 37-bit addition and subtraction unit shown in Equation4–1 and Figure4–2. For all signed numbers, input and output data is represented in 2’s-complement format only.Equation4–1.Multiplier Equation

P[36..0] = A0[17..0] × B0[17..0] ± A1[17..0] × B1[17..0]

Figure4–2.Basic Two-Multiplier Adder Building Block

A0[17..0]

B0[17..0]

+/-P[36..0]

A1[17..0]

DQB1[17..0]

DQThe structure shown in Figure4–2 is useful for building more complex structures, such as complex multipliers and 36×36 multipliers, as described in later sections.Each ArriaII DSP block contains four two-multiplier adder units

(2 two-multiplier adder units per half block). Therefore, there are eight 18×18 multiplier functionalities per DSP block. For a detailed diagram of the DSP block, refer to Figure4–5 on page4–8.

Following the two-multiplier adder units are the pipeline registers, the second-stage adders, and an output register stage. You can configure the second-stage adders to provide the alternative functions shown in Equation4–1 and Equation4–2 per half block.

Equation4–2.Four-Multiplier Adder Equation

Z[37..0] = P0[36..0] + P1[36..0]

Arria II Device Handbook Volume 1: Device Interfaces and Integration

Chapter 4:DSP Blocks in ArriaII DevicesSimplified DSP Operation

Equation4–3.Four-Multiplier Adder Equation (44-Bit Accumulation)

Wn[43..0] = Wn-1[43..0] ± Zn[37..0]

In these equations, n denotes sample time and P[36..0] are the results from the two-multiplier adder units.

Equation4–2 provides a sum of four 18×18-bit multiplication operations

(four-multiplier adder), and Equation4–3 provides a four 18×18-bit multiplication operation, but with a maximum of a 44-bit accumulation capability by feeding the output from the output register bank back to the adder/accumulator block, as shown in Figure4–3.

You can bypass all register stages depending on which mode you select, except

accumulation and loopback mode. In these two modes, you must enable at least one set of the registers. If the register is not enabled, an infinite loop occurs.

Figure4–3.Four-Multiplier Adder and Accumulation Capability

+InputDataAdder/Accumulator144Pipeline Register BankOutput Register BankInput Register Bank44Result[]Half-DSP BlockTo support FIR-like structures efficiently, a major addition to the DSP block in ArriaII devices is the ability to propagate the result of one half block to the next half block completely in the DSP block without additional soft logic overhead. This is achieved by the inclusion of a dedicated addition unit and routing that adds the 44-bit result of a previous half block with the 44-bit result of the current block. The 44-bit result is either fed to the next half block or out of the DSP block with the output register stage shown in Figure4–4. Detailed examples are described in later sections.

+Arria II Device Handbook Volume 1: Device Interfaces and Integration

FPGA可编程逻辑器件芯片EP2AGX95EF35C6N中文规格书 - 图文

AIIGX51004-4.0ArriaIIDeviceHandbookVolume1:DeviceInterfacesandIntegrationDecember2010Chapter4:DSPBlocksinArriaIIDevicesDSPBlockOverviewArriaIIDeviceH
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