Chapter4
User Primitives
The following configuration primitives are provided for users to access FPGA configuration resources during or after FPGA configuration.
BSCAN_VIRTEX5
JTAG is a standard four-pin interface: TCK, TMS, TDI, and TDO. Many applications are built around this interface. The JTAG TAP controller is a dedicated state machine inside the configuration logic. BSCAN_VIRTEX5 provides access between the JTAG TAP controller and user logic in fabric. There are up to four instances of BSCAN_VIRTEX5 for each device, each instance is controlled with the JTAG_CHAIN parameter. Table4-1 lists the BSCAN_VIRTEX5 fabric pins.
Table 4-1:BSCAN_VIRTEX5 Pin TablePin Name SEL
TypeOutput
Description
Active-High interface selection output. SEL=1 when the JTAG instruction register holds the corresponding USER1-4
instruction. Change in Update_IR state. SEL changes on the falling edge of TCK in the UPDATE_IR state of the TAP controller.
Active-High reset output. RESET=1 during the TEST-LOGIC-RESET state, PROGRAM_B, or during power up. This signal is deasserted on the falling edge of TCK.Fed through directly from the FPGA TDI pin.
DRCK is the same as TCK in the Capture_DR and Shift_DR states. If the interface is not selected by the instruction register, DRCK remains High.
Active-High pulse indicating the Capture_DR state. This signal is asserted on the falling edge of TCK.
Active-High pulse indicating the Update_DR state. This signal is asserted on the falling edge of TCK.
Active-High pulse indicating the Shift_DR state. This signal is asserted on the falling edge of TCK.
TDO input driven from the user fabric logic. This signal is internally sampled on the falling edge before being driven out to the FPGA TDO pin.
RESETOutput
TDIDRCK
OutputOutput
CAPTUREUPDATESHIFTTDO
OutputOutputOutputInput
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Chapter 4:User Primitives
CAPTURE_VIRTEX5
The CAPTURE_VIRTEX5 primitive is used to capture I/O, CLB, and block RAM output flip-flop status, and then read back through the configuration interface. The CAP input is sampled by CLK to generate an internal gcap signal. The I/O and CLB flip-flop status are captured into an FPGA configuration memory cell when the gcap signal is High. There are operation modes, a one-shot mode, or a continuous mode.
In one-shot mode, after the first CAP falling edge, gcap is held to 0 to avoid further capturing. An explicit RCAP command is required to re-arm the capture circuit.In continuous mode, the CAP input is simply sampled by CLK, and becomes the gcap signal, allowing the user to control when to capture.
CAPTURE_VIRTEX5 should not operate simultaneously with the FRAME_ECC_VIRTEX5 primitive or the Readback CRC function (see Chapter9, “Readback CRC”) because capturing a value into configuration memory might cause a false error.Table 4-2:CAPTURE_VIRTEX5 Pin TablePin Name CLKCAP
TypeInputInput
Description
Clock for sampling the CAP input.
Active-High capture enable. The CAP input is sampled by the rising edge of CLK.
ICAP_VIRTEX5
The ICAP_VIRTEX5 primitive works the same way as the SelectMAP configuration
interface except it is on the fabric side, and ICAP has a separate read/write bus, as opposed to the bidirectional bus in SelectMAP. The general SelectMAP timing diagrams and the SelectMAP bitstream ordering information as described in the “SelectMAP Configuration Interface” section of this user guide are also applicable to ICAP. It allows the user to access configuration registers, readback configuration data, or partially reconfigure the FPGA after configuration is done.
ICAP has three data width selections through the ICAP WIDTH parameter: x8, x16, and x32.
The two ICAP ports cannot be operated simultaneously. The design must start from the top ICAP, then switch back and forth between the two. Table 4-3:ICAP_VIRTEX5 Pin TablePin Name CLKCEWRITEI[31:0]
TypeInputInputInputInput
ICAP interface clock
Active-Low ICAP interface select. Equivalent to CS_B in the SelectMAP interface.
0=WRITE, 1=READ. Equivalent to the RDWR_B signal in the SelectMAP interface.
ICAP write data bus. The bus width depends on
ICAP_WIDTH parameter. The bit ordering is identical to the SelectMAP interface. See SelectMap Data Ordering in Figure2-19.
Description
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Dynamic Reconfiguration of Functional Blocks
is presented simultaneously with the write address and DWE and DEN signals prior to the next positive edge of DCLK. The port asserts DRDY for one clock cycle when it is ready to accept more data. The timing requirements relative to DCLK for all the other signals are the same. The output data is not registered in the functional blocks. Output (read) data is available after some cycles following the cycle that DEN and DADDR are asserted. The availability of output data is indicated by the assertion of DRDY.
Figure5-4 and Figure5-5 show the timing relationships between the port signals for write and read operations. Absolute timing parameters, such as maximum DCLK frequency, setup time, etc., are defined in DS202, Virtex-5 Data Sheet: DC and Switching Characteristics.
DCLKDENDRDYDWE
DADDR[m:0]
DI[n:0]DO[n:0]
UG191_c5_04_050406
bbBB
Figure 5-4:Write Timing with Wait States
DCLKDENDRDYDWE
DADDR[m:0]
DI[n:0]DO[n:0]
AA
UG191_c5_05_050406
AA
Figure 5-5:Read Timing with Wait States
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 5:Dynamic Reconfiguration Port (DRP)
Virtex-5 FPGA Configuration Guide
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Chapter 6:Configuration Details
Virtex-5 FPGA Configuration Guide
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FPGA可编程逻辑器件芯片XC2S150-5FGG256C中文规格书 - 图文
