28.7 SPECIAL FUNCTION REGISTERS
28.7.1 REGISTER MAP
MIPI HSI Tx Controller Register Map Table
Table 28-4. Tx Controller Register Map Table
Register TX_STATUS_REG TX_CONFIG_REG Reseved
TX_INTMSK_REG TX_CHID_REG TX_DATA_REG
Address 0x7E006000 0x7E006004
Description
MIPI HSI Tx controller status register MIPI HSI Tx controller configuration register
Reset Value 0x00010000 0xFFFFFF02 0x00000000 0x00000000 0x8000001F 0x00000000 0x00000000 0x00000000
0x7E006008 Reserved register area 0x7E006010 0x7E006018 0x7E00601C
MIPI HSI Tx controller interrupt mask register MIPI HSI Tx controller channel ID register MIPI HSI Tx controller data register (FIFO input)
TX_INTSRC_REG 0x7E00600C MIPI HSI Tx controller interrupt source register TX_SWRST_REG 0x7E006014 Tx controller software reset
MIPI HSI Rx Controller Register Map Table
Table 28-5. Rx Controller Register Map Table
Register RX_STATUS_REG RX_CONFIG0_REG RX_CONFIG1_REG RX_INTMSK_REG RX_CHID_REGRX_DATA_REG
Address 0x7E007000 0x7E007004 0x7E007008 0x7E007010
Description
MIPI HSI Rx controller status register MIPI HSI Rx controller configuration register MIPI HSI Rx controller configuration register MIPI HSI Rx controller interrupt mask register
Reset Value 0x00010000 0x0FFFFF02 0x00FFFFFF 0x00000000 0x800001FF 0x00000000 0x00000000 0x00000000
RX_INTSRC_REG 0x7E00700C MIPI HSI Rx controller interrupt source register RX_SWRST_REG 0x7E007014 Rx controller software reset
0x7E007018 MIPI HSI Rx controller channel ID register 0x7E00701C
MIPI HSI Rx controller data register (FIFO output)
MIPI HSI 6410X_UM
28.8 INDIVIDUAL REGISTER DESCRIPTIONS (TX CONTROLLER)
28.8.1 TX_STATUS_REG
TX_STATUS_REG is an internal logic monitoring window.
Table 28-6. TX_STATUS_REG register description
Register
TX_STATUS_REG
Address 0x7E00_6000
R/W R
Description
MIPI HSI Tx controller status register
Reset Value0x00010000
Bits [31][27]
Name
reserved Reserved bitreserved Reserved bit
Description R/W RR RR R R
Reset Value
0x00x0 0x00x0 0x00 0x00x10x0 0x00 0x00x00
[30:28] next_state Next state* [26:24] current state Current state* [23:18] reserved Reserved bits [17]
FIFO_full TxFIFO full
0 : FIFO not full
[16] FIFO_empty TxFIFO empty
0 : FIFO not empty
[15:13] reserved Reserved bits [12:8] tx_rd_point TxFIFO read point [7:5][4:0]
reserved Reserved bitstx_wr_point
TxFIFO write point
1 : FIFO empty 1 : FIFO full
RR R RR
?State register value000 : IDLE010 : Tx100 : TxIDLE110 : TxBRK
001 : TxREQ 011 : TxHOLD 101 : Reserved state 111 : TxERR
6410X_UMMIPI HSI
28.8.2 TX_CONFIG_REG
CONFIG_REG is used to set the configuration of Tx controller.
Table 28-7. TX_CONFIG_REG register description
Register
Address
R/W
Description
Reset Value0xFFFFFF02
TX_CONFIG_REG 0x7E00_6004 R/W MIPI HSI Tx controller configuration register Bits [31:24] [23:16] [15:8] [7] [6] [5] [4] [3:2] [1]
Name TxHOLD time TxIDLE time TxREQ time TxHOLD time_enTxIDLE time_en TxREQ time_en
Err_clr Width of CHID Burst_mode
Description
TxHOLD state timer setting value TxIDLE state timer setting value TxREQ state timer setting value TxHOLD state timer enabler 0 : disable0 : disable0 : disable
Generated Error clear 0 : stay
Width of channel ID Fixed channel ID mode
0 : Burst ch ID mode 1 : Single ch ID mode
1 : clear 1 : enable
TxIDLE state timer enabler
1 : enable
TxREQ state timer enabler
1 : enable
R/W R/W R/W R/W
Reset Value
0xFF 0xFF 0xFF
R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W
0x0
R/W 0x1 R/W 0x0 1 : Frame mode
[0] Frame_mode Frame mode
0 : Stream mode
28.8.3 TX_INTSRC_REG
INTSRC_REG is interrupt source pending register.
Table 28-8. TX_INTSRC_REG register description
Register
Address
R/W
Description
Reset Value0x00000000
TX_INTSRC_REG 0x7E00_600C R/W MIPI HSI Tx controller interrupt source register Bits [4] [3] [2]
Name TxH_timeout TxI_timeout TxR_timeout
Description
TxHOLD state timeout interrupt (set ‘1’ for clearing) TxIDLE state timeout interrupt (set ‘1’ for clearing) TxREQ state timeout interrupt (set ‘1’ for clearing)
R/W R R/W R/W R/W
Reset Value0x0000001
0x0 0x0 0x0
[31:5] Reserved Reserved bits
MIPI HSI 6410X_UM
6410X_UMMIPI HSI
28.8.5 TX_SWRST_REG SWRST_REG is software reset.
Table 28-10. TX_SWRST_REG register description
Register
Address
R/W
Description
Tx controller software reset Description
Software reset
0 : set 1 : reset
R/W R
Reset Value0x00000000 Reset Value0x00000000
TX_SWRST_REG 0x7E00_6014 R/W Bits [0]
Name Sw_rst
[31:1] Reserved Reserved bits
R/W 0x0 28.8.6 TX_CHID_REG
CHID_REG is used to transfer channel ID.
Table 28-11. TX_CHID_REG register description
Register
Address
R/W
Description
MIPI HSI Tx controller channel ID register
Description
R/W
Reset Value0x00000000 Reset Value
TX_CHID_REG 0x7E00_6018 R/W Bits [31]
Name
Break_frame Break frame transfer in Frame mode
In auto clear mode, this bit is automatically cleared. But the other mode, TxDATA send ‘0’ stream during setting ‘1’ at br_frame_clr bit. Auto_clr
Break frame auto clear bit
0 : auto clear & TxBRK state end
1 : auto clear disable & TxBRK state continue
R/W/C 0x0 [30] R/W0x0
[29] Br_frame_clr Stop break frame continuing transfer [28:3] Reserved Reserved bits [2:0]
CHID Channel ID
W R R/W
0x0 0x0000000
0x0
NOTE: In order to send data , the TX_CHID_REG must be set first and then the data to be
transfered are pushed into the data fifo. The same channel ID is attached to each of the data when it sent through TxDATA. If the channel ID is different from the previous one, you must set the new channel ID into the
TX_CHID_REG before pushing data into the data fifo. Break frame is sent to Rx side when ‘1’ is inputted for the Break_frame bit in the frame mode. This bit is automatically cleared after the transmission is completed (36 ‘0’s
are transffered) in the auto clear mode (auto clear bit =0). In this case, the internal state goes to IDLE state. If not in the auto clear mode, the TxDATA continues to transfer ‘0’ while the internal state maintained in TxBRK state.
Meanwhile, if the br_frame_clr bit is written as ‘1’, the state changes from RxBRK to IDLE and the TxDATA stops to transfer ‘0’s.
MEMORY存储芯片S3C6410X66-YB40中文规格书 - 图文
