湘潭大学计算机原理实验四多周期MIPS CPU 存储器实验预习报告解析

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存储器内的测试数据：

-- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of

-- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details.

-- Quartus II generated Memory Initialization File (.mif)

DEPTH = 64; %Memory depth and width are required WIDTH = 32; %Enter a decimal number ADDRESS_RADIX = HEX; -dress and value radixes are optional DATA_RADIX = HEX; %Enter BIN, DEC, HEX, or OCT; unless %otherwise specified, radixes = HEX

CONTENT BEGIN

[0..3F] : 00000000; % Range--Every address from 0 to 3F = 00000000 0 : 3c010000; % (00) main: lui r1, 0 # address of data[0] 1 : 34240080; % (04) ori r4, r1, 0x80# address of data[0] 2 : 20050004; % (08) addi r5, r0, 4 # counter 3 : 0c000018; % (0c) call: jal sum # call function 4 : ac820000; % (10) sw r2, 0(r4) # store result 5 : 8c890000; % (14) lw r9, 0(r4) # check sw 6 : 01244022; % (18) sub r8, r9, r4 # sub: r8 <-- r9 - r4 7 : 20050003; % (1c) addi r5, r0, 3 # counter 8 : 20a5ffff; % (20) loop2: addi r5, r5,-1 # counter - 1 9 : 34a8ffff; % (24) ori r8, r5, 0xffff # zero-extend: 0000ffff A : 39085555; % (28) xori r8, r8, 0x5555 # zero-extend: 0000aaaa B : 2009ffff; % (2c) addi r9, r0, -1 # sign-extend: ffffffff C : 312affff; % (30) andi r10,r9, 0xffff # zero-extend: 0000ffff D : 01493025; % (34) or r6, r10,r9 # or: ffffffff E : 01494026; % (38) xor r8, r10,r9 # xor: ffff0000 F : 01463824; % (3c) and r7, r10,r6 # and: 0000ffff 10 : 10a00001;% (40) beq r5, r0, shift # if r5 = 0, goto shift 11 : 08000008;% (44) j loop2 # jump loop2 12 : 2005ffff; % (48) shift: addi r5, r0, -1 # r5 = ffffffff %

% % % %

% % % % % % % % % % % % % % % % % % % %

13 : 000543c0;% (4c) 14 : 00084400;% (50) 15 : 00084403;% (54) 16 : 000843c2;% (58) 17 : 08000017;% (5c) 18 : 00004020;% (60) 19 : 8c890000;% (64) 1A : 20840004;% (68) 1B : 01094020;% (6c) 1C : 20a5ffff; % (70) 1D : 14a0fffb; % (74) 1E : 00081000;% (78) 1F : 03e00008;% (7c) 20 : 000000A3;% (80) 21 : 00000027;% (84) 22 : 00000079;% (88) 23 : 00000115;% (8c) 24 : 00000000;% (90) END;

finish: sum: loop: data[0] data[1] data[2] data[3] sum sll sll sra srl j add lw addi r4, add addi r5, bne sll jr r8, r5, 15 # <<15 = ffff8000

r8, r8, 16 # <<16 = 80000000 r8, r8, 16 # >>16 = ffff8000(arith) r8, r8, 15 # >>15 = 0001ffff(logic) finish # dead loop r8, r0, r0 # sum r9, 0(r4) # load data r4, 4 # address + 4 r8, r8, r9 # sum r5, -1 # counter - 1 r5, r0, loop # finish? r2, r8, 0 # move result to v0 r31 # return %

% % % % % % % % % % % % % % % % %

六．EDA阶段的实验结果（ “编译”、 “仿真” 等）

仿真结果如上图。

七．测试时的电路总体结构及其说明

实验电路图

八．测试计划（包括计划进行的系统测试、每一测试的测试过程、测试所需的测试数据、预期结果数据等）及其相关说明

输出说明：

由于引脚及输出需要，故下表ir对应ir[31..0]且将显示高四位，pc对应pc[31..0]且将显示低两位，alu对应alu[31..0]且将显示低两位

输入 clock mem_clk pc 输出 alu ir clock 输入 mem_clk pc 输出 alu ir

九．关于实验电路设计的其他说明

由于引脚及输出需要，故只输出ir、pc、aluir[31..0]切将显示ir高四位，pc[31..0]低两位，alu[31..0]低两位,q、adr、fromm、a、b、tom将不会输出

十．前期实验总结