湘潭大学计算机原理实验四多周期MIPS CPU 存储器实验预习报告解析

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jal = 0; // not a jal sext = 1; // sign extend

case (state) //----------------------------------------------------- IF: sif: begin // IF state wpc = 1; // write pc wir = 1; // write IR alusrca = 1; // PC alusrcb = 2'h1; // 4 next_state = sid; // next state: ID end //----------------------------------------------------- ID: sid: begin // ID state if (i_j) begin // j instruction pcsource = 2'h3; // jump address wpc = 1; // write PC next_state = sif; // next state: IF end else if (i_jal) begin // jal instruction pcsource = 2'h3; // jump address wpc = 1; // write PC jal = 1; // reg no = 31 wreg = 1; // save PC+4 next_state = sif; // next state: IF end else if (i_jr) begin // jr instruction pcsource = 2'h2; // jump register wpc = 1; // write PC next_state = sif; // next state: IF end else begin // other instruction aluc = 4'bx000; // add alusrca = 1; // PC alusrcb = 2'h3; // branch offset next_state = sexe; // next state: EXE end end //----------------------------------------------------- EXE: sexe: begin // EXE state aluc[3] = i_sra; aluc[2] = i_sub | i_or | i_srl | i_sra | i_ori | i_lui ;

i_lui ;

aluc[0] = i_and | i_or | i_sll | i_srl | i_sra | i_andi | i_ori ; if (i_beq || i_bne) begin // beq or bne instruction pcsource = 2'h1; // branch address wpc = i_beq & z | i_bne & ~z; // write PC next_state = sif; // next state: IF end else begin // other instruction if(i_lw || i_sw) begin // lw or sw instruction alusrcb = 2'h2; // select offset next_state = smem; // next state: MEM end else begin // other instruction if (i_shift) shift = 1; // shift instruction if (i_addi || i_andi || i_ori || i_xori || i_lui) alusrcb = 2'h2; // select immediate if (i_andi || i_ori || i_xori) sext = 0; // 0-extend next_state = swb; // next state: WB end end end

//----------------------------------------------------- MEM: smem: begin // MEM state iord = 1; // memory address = C if (i_lw) begin next_state = swb; // next state: WB end else begin // store wmem = 1; // write memory next_state = sif; // next state: IF end end

//----------------------------------------------------- WB: swb: begin // WB state if (i_lw) m2reg = 1; // select memory data if (i_lw || i_addi || i_andi || i_ori || i_xori || i_lui) regrt = 1; // reg dest no: rt wreg = 1; // write register file next_state = sif; // next state: IF

end //----------------------------------------------------- END default: begin next_state = sif; end endcase end always @ (posedge clock or negedge resetn) begin if (resetn == 0) begin state <= sif; end else begin state <= next_state; end end endmodule

32位带使能端触发器： module dffe32 (d,clk,clrn,e,q); input [31:0] d; input clk,clrn,e; output [31:0] q; reg [31:0] q; always @ (negedge clrn or posedge clk) if (clrn == 0) begin q <= 0; end else begin if(e == 1) q <= d; end endmodule

32位触发器：

module dff32 (d,clk,clrn,q); input [31:0] d; input clk,clrn; output [31:0] q; reg [31:0] q; always @ (negedge clrn or posedge clk) if (clrn == 0) begin q <= 0;

//default state // state registers

end else begin q <= d; end endmodule

ALU计算部件：

module alu (a,b,aluc,r,z); input [31:0] a,b; input [3:0] aluc; output [31:0] r; output z; assign r = cal(a,b,aluc); assign z = ~|r; function [31:0] cal; input [31:0] a,b; input [3:0] aluc; casex (aluc) 4'bx000: cal=a+b; 4'bx100: cal=a-b; 4'bx001: cal=a&b; 4'bx101: cal=a|b; 4'bx010: cal=a^b; 4'bx110: cal={b[15:0],16'h0}; 4'bx011: cal=b<>a[4:0]; 4'b1111: cal=$signed(b)>>>a[4:0]; endcase endfunction endmodule

其他部件：

module f (reg_dest,jal,wn); input [4:0] reg_dest; input jal; output [4:0] wn; assign wn = reg_dest | {5{jal}}; endmodule

module sa (di,dot); input [4:0] di; output [31:0] dot; assign dot = {27'b0,di}; endmodule

module out4 (out); output [31:0] out; assign out = 32'h4; endmodule

module e (immin,sext,immediate,offset); input [15:0] immin; input sext; output [31:0] immediate,offset; wire e = sext & immin[15]; wire [15:0] imm = {16{e}}; assign offset = {imm[13:0],immin[15:0],1'b0,1'b0}; assign immediate = {imm,immin[15:0]}; endmodule

module combine (address,pc,add); input [25:0] address; input [3:0] pc; output [31:0] add; assign add = {pc[3:0],address[25:0],1'b0,1'b0}; endmodule

module convert1 (dain,sain,op,func,rs,rt,rd,imm,addr); input [31:0] dain; output [4:0] sain,rs,rt,rd; output [5:0] op,func; output [15:0] imm; output [25:0] addr; assign sain = {dain[10:6]}; assign op = {dain[31:26]}; assign func = {dain[5:0]}; assign rs = {dain[25:21]}; assign rt = {dain[20:16]}; assign rd = {dain[15:11]}; assign imm = {dain[15:0]}; assign addr = {dain[25:0]}; endmodule

module convert2 (pc,pcout); input [31:0] pc; output [3:0] pcout; assign pcout = {pc[31:28]}; endmodule