Feature Descriptions
DDR3 Memory
[Figure1-2, callout 2]
The memory module at J1 is a 1GB DDR3 small outline dual-inline memory module (SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM) for storing user code and data.?????
Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)Supply voltage: 1.5V
Configuration: 1GB (128 Mb x 64)Datapath width: 64bitsData rate: Up to 1,600MT/s
The VC707 XC7VX485T FPGA memory interface performance is documented in the Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics (DS183) [Ref2].
The DDR3 interface is implemented across I/O banks 37, 38, and 39. Each bank is a 1.5V
high-performance bank having a dedicated DCI VRP/N resistor connection. An external 0.75V reference VTTREF is provided for data interface banks 37 and 39. Any interface connected to these banks that requires a reference voltage must use this FPGA voltage reference. The connections between the DDR3 memory and the FPGA are listed in Table1-4.
Table 1-4:
DDR3 Memory Connections to the FPGA
Net NameDDR3_A0DDR3_A1DDR3_A2DDR3_A3DDR3_A4DDR3_A5DDR3_A6DDR3_A7DDR3_A8DDR3_A9DDR3_A10DDR3_A11DDR3_A12DDR3_A13DDR3_A14DDR3_A15DDR3_BA0DDR3_BA1
I/O StandardSSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15
J1 DDR3 Memory
Pin Number
9897969592919086898510784831198078109108
Pin Name
A0A1A2A3A4A5A6A7A8A9A10/APA11A12_BC_N
A13A14A15BA0BA1
FPGA (U1) Pin
A20B19C20A19A17A16D20C18D17C19B21B17A15A21F17E17D21C21
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Feature Descriptions
Clock Generation
The VC707 board provides five clock sources for the FPGA. Table1-9 lists the source devices for each clock.
Table 1-9:
VC707 Board Clock Sources
ClockSourceU51U34J31J32J25J26U24
Description
SiT9102 2.5V LVDS 200MHz Fixed Frequency Oscillator (SiTime).See System Clock (SYSCLK_P and SYSCLK_N).
Si570 3.3V LVDS I2C Programmable Oscillator, 156.250MHz default (Silicon Labs).See Programmable User Clock (USER_CLOCK_P and USER_CLOCK_N).USER_SMA_CLOCK_P (Net name).
See User SMA Clock (USER_SMA_CLOCK_P and USER_SMA_CLOCK_N).USER_SMA_CLOCK_N (Net name).
See User SMA Clock (USER_SMA_CLOCK_P and USER_SMA_CLOCK_N).SMA_MGT_REFCLK_C_P (Net name).
See GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N).SMA_MGT_REFCLK_C_N (Net name).
See GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N).Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs).See Jitter Attenuated Clock.
Clock NameSystem ClockUser Clock
User SMA Clock(differential pair)
GTX SMA REF Clock(differential pair)Jitter Attenuated
Clock
Table1-10 lists the pin-to-pin connections from each clock source to the FPGA.
Table 1-10:
Clock Connections, Source to FPGA
Net Name SYSCLK_NSYSCLK_PUSER_CLOCK_NUSER_CLOCK_PSMA_MGT_REFCLK_NSMA_MGT_REFCLK_PUSER_SMA_CLOCK_NUSER_SMA_CLOCK_P
Si5324_OUT_NSi5324_OUT_P
I/O Standard
LVDSLVDSLVDSLVDS
N/A (MGT REFCLK INPUT)N/A (MGT REFCLK INPUT)
LVCMOS18LVCMOS18
N/A (MGT REFCLK INPUT)N/A (MGT REFCLK INPUT)
FPGA (U1) Pin
E18E19AL34AK34AK7AK8AK32AJ32AD7AD8
Clock Source Pin
U51.5U51.4U34.5U34.4J26.1J25.1J32.1J31.1U24.29U24.28
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Feature Descriptions
SGMII GTX Transceiver Clock Generation
[Figure1-2, callout 16]
An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter, 125MHz LVDS clock from a 25MHz crystal (X3). This clock is sent to FPGA U1, Bank 113 GTX
transceiver (clock pins AH8 (P) and AH7 (N)) driving the SGMII interface. Series AC coupling capacitors are present to allow the clock input of the FPGA to set the common mode voltage. Figure1-17 shows the Ethernet SGMII clock source.
X-Ref Target - Figure 1-17C30018pF 50VNPOVDDA_SGMIICLKVDD_SGMIICLKU2X325.00 MHz1X11SGMIICLK_XTAL_OUT3ICS844021I-01Clock GeneratorOEVDDAXTAL_OUTVDDQ0587SGMIICLK_Q0_C_PR3201.0MΩ 5?0118pF 50VNPO2GND2C280.1μF 25VX5RSGMIICLK_Q0_P4GND2X23SGMIICLK_XTAL_IN42XTAL_INGNDNQ06SGMIICLK_Q0_C_NSGMIICLK_Q0_NC290.1μF 25VX5RUG885_c1_17_020612GND_SGMIICLKGND_SGMIICLKGND_SGMIICLKFigure 1-17:Ethernet 125 MHz SGMII GTX Clock
References
Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode Ethernet MAC Product Guide for Vivado Design Suite (PG051) [Ref9] and in the LogiCORE IP Tri-Mode Ethernet MAC v4.5 User Guide (UG138) [Ref13].
The product brief for the Marvell 88E1111 Alaska Gigabit Ethernet Transceiver can be found at the Marvell website [Ref21].
The data sheet can be obtained under NDA with Marvell. Contact information is at the Marvell website [Ref21].
For more information about the ICS844021 device, go to the Integrated Device Technology website [Ref22] and search for part number ICS844021.
USB-to-UART Bridge
[Figure1-2, callout 17]
The VC707 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U44) which allows a connection to a host computer with a USB port. The USB cable is supplied in the VC707 Evaluation Kit (Type-A end to host computer, Type mini-B end to VC707 board connector J17). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the VC707 board.
Xilinx UART IP is expected to be implemented in the FPGA logic. The FPGA supports the
USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications application software (for example, TeraTerm) that runs on the host computer. The VCP device
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
FPGA可编程逻辑器件芯片XC2V3000-4FG676I中文规格书
