FPGA可编程逻辑器件芯片AD822ARZ-REEL7中文规格书 - 图文

Data Sheet

FEATURES

True single-supply operation Output swings rail-to-rail

Input voltage range extends below ground Single-supply capability from 5 V to 30 V Dual-supply capability from ±2.5 V to ±15 V High load drive

Capacitive load drive of 350 pF, G = +1 Minimum output current of 15 mA Excellent ac performance for low power

800 μA maximum quiescent current per amplifier Unity-gain bandwidth: 1.8 MHz Slew rate of 3 V/μs Good dc performance

800 μV maximum input offset voltage 2 μV/°C typical offset voltage drift 25 pA maximum input bias current Low noise

13 nV/√Hz at 10 kHz No phase inversion

APPLICATIONS

Battery-powered precision instrumentation Photodiode preamps Active filters

12-bit to 14-bit data acquisition systems Medical instrumentation

Low power references and regulators

GENERAL DESCRIPTION

The AD822 is a dual precision, low power FET input op amp that can operate from a single supply of 5 V to 30 V or from dual supplies of ±2.5 V to ±15 V. It has true single-supply capability with an input voltage range extending below the negative rail, allowing the AD822 to accommodate input signals below ground while in the single-supply mode. Output voltage swing extends to within 10 mV of each rail, providing the maximum output dynamic range.

Offset voltage of 800 μV maximum, offset voltage drift of 2 μV/°C, input bias currents below 25 pA, and low input voltage noise provide dc precision with source impedances up to a gigaohm. The 1.8 MHz unity-gain bandwidth, –93 dB total harmonic distortion (THD) at 10 kHz, and 3 V/μs slew rate are provided with a low supply current of 800 μA per amplifier.

AD822

CONNECTION DIAGRAM

OUT118V+–IN127OUT2+IN136–IN210V–4AD8225+IN20-47800Figure 1. 8-Lead PDIP (N Suffix); 8-Lead MSOP (RM Suffix); and 8-Lead SOIC_N (R Suffix)

100)zH√/Vn( ESION EG10ALTOV TUPNI120101001k10k0-47FREQUENCY (Hz)800Figure 2. Input Voltage Noise vs. Frequency

AD822 SPECIFICATIONS

VS = 0 V, 5 V at TA = 25°C, VCM = 0 V, VOUT = 0.2 V, unless otherwise noted. Table 1.

Parameter

DC PERFORMANCE Initial Offset

Maximum Offset Over Temperature Offset Drift

Input Bias Current At TMAX

Input Offset Current At TMAX

Open-Loop Gain

TMIN to TMAX

RL = 10 k?

TMIN to TMAX

RL = 1 k?

TMIN to TMAX

NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz

Input Current Noise f = 0.1 Hz to 10 Hz f = 1 kHz

Harmonic Distortion f = 10 kHz

DYNAMIC PERFORMANCE Unity-Gain Frequency Full Power Response Slew Rate Settling Time To 0.1% To 0.01%

MATCHING CHARACTERISTICS Initial Offset

Maximum Offset Over Temperature Offset Drift Input Bias Current Crosstalk @ f = 1 kHz Crosstalk @ f = 100 kHz

Test Conditions/Comments

Min

A Grade Typ Max 0.1 0.5 2 2 0.5 2 0.5

500 400 80 80 15 10

1000 150 30

0.8 1.2 25 5 20

Min

Data Sheet

B Grade Typ Max 0.1 0.5 2 2 0.5 2 0.5

0.4 0.9 10 2.5 10

Unit mV mV μV/°C pA nA pA nA V/mV V/mV V/mV V/mV V/mV V/mV

VCM = 0 V to 4 V

VOUT = 0.2 V to 4 V RL = 100 k?

500 400 80 80 15 10

1000 150 30

2 25 21 16 13 18 0.8

RL = 10 k? to 2.5 V VOUT = 0.25 V to 4.75 V

?93 1.8 210 3 1.4 1.8

1.0 1.6

3

20

RL = 5 k? RL = 5 k?

?130 ?93

2 25 21 16 13 18 0.8 ?93 1.8 210 3 1.4 1.8

0.5 1.3

3

10

–130–93

μV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA p-p fA/√Hz dB MHz kHz V/μs μs μs mV mV μV/°C pA dB dB

VOUT p-p = 4.5 V

VOUT = 0.2 V to 4.5 V VOUT = 0.2 V to 4.5 V

Rev. J | Page 4 of 24

Data Sheet

Parameter

INPUT CHARACTERISTICS

Input Voltage Range1, TMIN to TMAX

Common-Mode Rejection Ratio (CMRR) TMIN to TMAX Input Impedance Differential Common Mode

OUTPUT CHARACTERISTICS Output Saturation Voltage2 VOL ? VEE

TMIN to TMAX VCC ? VOH TMIN to TMAX VOL ? VEE TMIN to TMAX VCC ? VOH TMIN to TMAX VOL – VEE

TMIN to TMAX VCC ? VOH TMIN to TMAX

Operating Output Current TMIN to TMAX

Capacitive Load Drive POWER SUPPLY

Quiescent Current, TMIN to TMAX Power Supply Rejection TMIN to TMAX

1

AD822

Test Conditions/Comments

Min ?0.2 66 66

A Grade Typ Max

+4

80

Min ?0.2

69 66

B Grade Typ Max

+4

80

Unit V

dB dB ?||pF ?||pF

VCM = 0 V to 2 V VCM = 0 V to 2 V

1013||0.5 1013||2.8 1013||0.5 1013||2.8

ISINK = 20 μA ISOURCE = 20 μA ISINK = 2 mA ISOURCE = 2 mA ISINK = 15 mA ISOURCE = 15 mA

15 12

5 10 40 80 300 800

7 10 14 20 55 80 110 160 500 1000 1500 1900

15 12

5 10 40 80 300 800

7 10 14 20 55 80 110 160 500 1000 1500 1900

350 1.24 80

1.6

70 70

350 1.24 80

1.6

mV mV mV mV mV mV mV mV mV mV mV mV mA mA pF mA dB dB

V+ = 5 V to 15 V

66 66

This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ ? 1 V) to V+. Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply. 2

VOL ? VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC ? VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC).

Rev. J | Page 5 of 24

AD822

ABSOLUTE MAXIMUM RATINGS

Table 4.

ParametergRatinSupply Voltage ±18 V Internal Power Dissipation 8-Lead PDIP (N) Observe derating curves 8-Lead SOIC_N (R) Observe derating curves 8-Lead MSOP (RM) Observe derating curves Input Voltage1 ((V+) + 0.2 V) to

((V?) ? 20 V)

Output Short-Circuit Duration Indefinite Differential Input Voltage ±30 V Storage Temperature Range (N) –65°C to +125°C Storage Temperature Range (R, RM) –65°C to +150°C Operating Temperature Range A Grade and B Grade –40°C to +85°C

260°C Lead Temperature

(Soldering, 60 sec)

Data Sheet

THERMAL RESISTANCE

θJA is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance

Package Type 8-lead PDIP (N) 8-lead SOIC_N (R) 8-lead MSOP (RM)

θJA90 160 190

Unit°C/W °C/W °C/W

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD822 is limited by the associated rise in junction temperature. For plastic packages, the maximum safe junction temperature is 145°C. If these maximums are exceeded momentarily, proper circuit operation is restored as soon as the die temperature is reduced. Leaving the device in the overheated condition for an extended period can result in device burnout. To ensure proper operation, it is important to observe the derating curves shown in Figure 27.

AD822

Data Sheet

100kWHENEVERJOHNSONNOISEISGREATERTHANAMPLIFIERNOISE,AMPLIFIERNOISECANBECONSIDEREDNEGLIGIBLEFORAPPLICATION.1kHz1kRESISTOR JOHNSONNOISEAPPLICATIONS INFORMATION

INPUT CHARACTERISTICS

In the AD822, N-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input common-mode voltage extends from 0.2 V below ?VS to 1 V less than +VS. Driving the input voltage closer to the positive rail causes a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in Figure 34 and Figure 37) and increased common-mode voltage error as illustrated in Figure 20. The AD822 does not exhibit phase reversal for input voltages up to and including +VS. Figure 42 shows the response of an AD822 voltage follower to a 0 V to 5 V (+VS) square wave input. The input and output are superimposed. The output tracks the input up to +VS without phase reversal. The reduced bandwidth above a 4 V input causes the rounding of the output waveform. For input voltages greater than +VS, a resistor in series with the AD822 noninverting input prevents phase reversal, at the expense of greater input voltage noise. This is illustrated in Figure 42. Because the input stage uses N-channel JFETs, input current during normal operation is negative; the current flows out from the input terminals. If the input voltage is driven more positive than +VS ? 0.4 V, then the input current reverses direction as internal device junctions become forward biased. This is illustrated in Figure 7.

A current-limiting resistor should be used in series with the input of the AD822 if there is a possibility of the input voltage exceeding the positive supply by more than 300 mV, or if an input voltage is applied to the AD822 when +VS or ?VS = 0 V. The amplifier is damaged if left in that condition for more than 10 seconds. A 1 k? resistor allows the amplifier to withstand up to 10 V of continuous overvoltage and increases the input voltage noise by a negligible amount.

Input voltages less than ?VS are different. The amplifier can safely withstand input voltages 20 V below the negative supply voltage if the total voltage from the positive supply to the input terminal is less than 36 V. In addition, the input stage typically maintains picoampere (pA) level input currents across that input voltage range.

The AD822 is designed for 13 nV/√Hz wideband input voltage noise and maintains low noise performance to low frequencies (refer to Figure 14). This noise performance, along with the AD822 low input current and current noise, means that the AD822 contributes negligible noise for applications with source resistances greater than 10 k? and signal bandwidths greater than 1 kHz. This is illustrated in Figure 43.

10kINPUT VOLTAGE NOISE (μV)1001010Hz1AMPLIFIER-GENERATEDNOISE100k10M100M1MSOURCE IMPEDANCE (?)1G10G00874-0430.110k

Figure 43. Total Noise vs. Source Impedance

OUTPUT CHARACTERISTICS

The AD822 unique bipolar rail-to-rail output stage swings within 5 mV of the negative supply and 10 mV of the positive supply with no external resistive load. The approximate output saturation resistance of the AD822 is 40 ? sourcing and 20 ? sinking, which can be used to estimate output saturation voltage when driving heavier current loads. For instance, when sourcing 5 mA, the saturation voltage to the positive supply rail is 200 mV; when sinking 5 mA, the saturation voltage to the negative rail is 100 mV. The open-loop gain characteristic of the amplifier changes as a function of resistive load, as shown in Figure 10 to Figure 13. For load resistances over 20 k?, the AD822 input error voltage is virtually unchanged until the output voltage is driven to 180 mV of either supply.

If the AD822 output is overdriven so that either of the output devices are saturated, the amplifier recovers within 2 μs of the input returning to the linear operating region of the amplifier. Direct capacitive loads interact with the effective output impedance of the amplifier to form an additional pole in the amplifier feedback loop, which can cause excessive peaking on the pulse response or loss of stability. The worst case occurs when the amplifier is used as a unity-gain follower. Figure 44 shows the AD822 pulse response as a unity-gain follower

driving 350 pF. This amount of overshoot indicates approximately 20° of phase margin—the system is stable, but nearing the edge. Configurations with less loop gain, and as a result less loop bandwidth, are much less sensitive to capacitance load effects.

Rev. J | Page 18 of 24