FPGA可编程逻辑器件芯片EP1SGX40FG1020C7N中文规格书

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Loopback Modes

The StratixGX transceiver has built-in loopback modes to aid in debug and testing. The loopback modes are set in the StratixGX MegaWizard Plug-In Manager in the QuartusII software. Only one loopback mode can be set at any single instance of the transceiver block. The loopback mode applies to all used channels in a transceiver block.The available loopback modes are:

■■■

Serial loopbackParallel loopback

Reverse serial loopback

Serial Loopback

Serial loopback exercises all the transceiver logic except for the output buffer and input buffer. The loopback function is dynamically switchable through the rx_slpbk port on a channel by channel basis. The VOD of the output is limited to 400mV when the serial loopback option is selected. Figure23 shows the data path in serial loopback mode.

Figure23.Data Path in Serial Loopback Mode

BIST PRBSVerifierDeserializerWordAlignerBISTIncrementalVerifierRateMatcher8B/10BDecoderPhaseCompensationFIFOChannelAlignerClockRecoveryUnitByteDeserializerSerializer8B/10BEncoderBIST PRBSGeneratorByteSerializerPhaseCompensationFIFOBISTGeneratorActive PathNon-active PathTransceiver Blocks

Parallel Loopback

The parallel loopback mode exercises the digital logic portion of the transceiver data path. The analog portions are not use in the loopback path. The received data is not retimed. Figure24 shows the data path in parallel loopback mode. This option is not dynamically switchable. Reception of an external signal is not possible in this mode.

Figure24.Data Path in Parallel Loopback Mode

The reverse serial loopback exercises the analog portion of the

transceiver. This loopback mode is dynamically switchable through the tx_srlpbk port on a channel by channel basis. Asserting

rxanalogreset in reverse serial loopback mode powers down the receiver buffer and CRU, preventing data loopback. Figure25 shows the data path in reverse serial loopback mode.

StratixGX FPGA Family

Figure25.Data Path in Reverse Serial Loopback Mode

BIST PRBSVerifierDeserializerWordAlignerBISTIncrementalVerifierRateMatcher8B/10BDecoderPhaseCompensationFIFOChannelAlignerClockRecoveryUnitByteDeserializerSerializer8B/10BEncoderBIST PRBSGeneratorByteSerializerPhaseCompensationFIFOActive PathNon-active PathBISTGeneratorBIST (Built-In Self Test)

The StratixGX transceiver has built-in self test modes to aid in debug and testing. The BIST modes are set in the StratixGX MegaWizard Plug-In Manager in the QuartusII software. Only one BIST mode can be set for any single instance of the transceiver block. The BIST mode applies to all channels used in a transceiver.

The following is a list of the available BIST modes:

■■■■■

PRBS generator and verifier

Incremental mode generator and verifierHigh-frequency generatorLow-frequency generatorMixed-frequency generator

Figures26 and 27 are diagrams of the BIST PRBS data path and the BIST incremental data path, respectively.

Transceiver Blocks

Figure26.BIST PRBS Data Path

Table14.BIST Data Output & Verifier Alignment Pattern (Part 1 of2)BIST Mode

PRBS 8-bitPRBS 10-bit

28 – 1210 – 1

OutputPolynomials

x8 + x7 + x5 + x3 + 1x10 + x7 + 1

Verifier Word Alignment Pattern

10000000111111111111111111

StratixGX FPGA Family

Table14.BIST Data Output & Verifier Alignment Pattern (Part 2 of2)BIST Mode

PRBS 16-bitPRBS 20-bitIncremental 10-bit

28 – 1210 – 1

K28.5, K27.7, Data (00-FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7, K30.7, K29.7 (1)K28.5, K27.7, Data (00-FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7, K30.7, K29.7 (1)10101010100011111000

0011111010 or 1100000101

OutputPolynomials

x8 + x7 + x5 + x3 + 1x10 + x7 + 1

Verifier Word Alignment Pattern

100000001111111111111111110101111100 (K28.5)

Incremental 20-bit0101111100 (K28.5)

High frequencyLow frequencyMixed frequency