AIIGX51001-4.4
The Arria? II device family is designed specifically for ease-of-use. The cost-optimized, 40-nm device family architecture features a low-power,
programmable logic engine and streamlined transceivers and I/Os. Common interfaces, such as the Physical Interface for PCI Express? (PCIe?), Ethernet, and
DDR3 memory are easily implemented in your design with the Quartus?II software, the SOPC Builder design software, and a broad library of hard and soft intellectual property (IP) solutions from Altera. The ArriaIIdevice family makes designing for applications requiring transceivers operating at up to 6.375Gbps fast and easy.This chapter contains the following sections:
■■■
“ArriaIIDevice Feature” on page1–1“Arria II Device Architecture” on page1–6
“Reference and Ordering Information” on page1–14
ArriaIIDevice Feature
The ArriaIIdevice features consist of the following highlights:
■
40-nm, low-power FPGA engine
■■■
Adaptive logic module (ALM) offers the highest logic efficiency in the industryEight-input fracturable look-up table (LUT)
Memory logic array blocks (MLABs) for efficient implementation of smallFIFOs
■
High-performance digital signal processing (DSP) blocks up to 550MHz
■
Configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precisionmultipliers as well as 18 x 36-bit high-precision multiplier
Hardcoded adders, subtractors, accumulators, and summation functionsFully-integrated design flow with the MATLAB and DSP Builder softwarefrom Altera
■■
■
Maximum system bandwidth
■
Up to 24 full-duplex clock data recovery (CDR)-based transceivers supportingrates between 600Mbps and 6.375Gbps
Dedicated circuitry to support physical layer functionality for popular serialprotocols, including PCIe Gen1 and PCIeGen2, GbpsEthernet, SerialRapidIO? (SRIO), Common Public Radio Interface (CPRI), OBSAI,
SD/HD/3G/ASI Serial Digital Interface (SDI), XAUI and Reduced XAUI(RXAUI), HiGig/HiGig+, SATA/Serial Attached SCSI (SAS), GPON,
SerialLiteII, Fiber Channel, SONET/SDH, Interlaken, Serial Data Converter(JESD204), and SFI-5.
■
Arria II Device Handbook Volume 1: Device Interfaces and IntegrationJuly 2012
Chapter 1:Overview for the Arria II Device Family
ArriaIIDevice Feature
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 1:Overview for the Arria II Device Family
ArriaIIDevice Feature
Table1–2 and Table1–3 list the ArriaII device package options and user I/O pin counts, high-speed LVDS channel counts, and transceiver channel counts for Ultra FineLine BGA (UBGA) and FineLine BGA (FBGA) devices.
Table1–2.Package Options and I/O Information for ArriaIIGX Devices
358-Pin Flip Chip UBGA
17 mm x 17 mm
XCVRsDevice
I/O
LVDS (8)
572-Pin Flip Chip FBGA
25 mm x 25 mm
XCVRsI/O
LVDS (8)57(RD or eTX) + 56(RX, TX, or eTX)57(RD or eTX) + 56(RX, TX, or eTX)57(RD or eTX) + 56(RX, TX, or eTX)57(RD or eTX) + 56(RX,TX, or
eTX)
—
(Note1), (2), (3), (4), (5), (6), (7)780-Pin Flip Chip FBGA
29 mm x 29 mm
XCVRsI/O
LVDS (8)85(RD or eTX) +84(RX, TX,or eTX)85(RD or eTX) +84(RX,TX,eTX)85(RD or eTX) +84(RX, TX, or
eTX)85(RD or eTX) +84(RX,TX, or
eTX)85(RD or eTX) +84(RX, TX, or
eTX)85(RD, eTX) +84(RX, TX, or
eTX)
1152-Pin Flip Chip FBGA
35 mm x 35 mmI/O
LVDS (8)
XCVRs——12121616
EP2AGX45
33(RD or eTX) 156+32(RX, TX,
or eTX)33(RD or eTX) 156+32(RX, TX,
or eTX)
425283648——
EP2AGX65425283648——105(RD or eTX) + 104(RX, TX, or
eTX)105(RD or eTX) + 104(RX, TX, or
eTX)145(RD or eTX) + 144(RX, TX, or
eTX)
EP2AGX95———260837212452
EP2AGX125———260837212452
EP2AGX190—————37212612
EP2AGX260——————37212
145(RD, eTX) + 612144(RX, TX, or
eTX)
Notes to Table1–2:
(1)The user I/O counts include clock pins.
(2)The arrows indicate packages vertical migration capability. Vertical migration allows you to migrate to devices whose dedicated pins, configuration pins,
and power pins are the same for a given package across device densities.(3)RD = True LVDS input buffers with on-chip differential termination (RDOCT) support.(4)RX = True LVDS input buffers without RDOCT support.(5)TX = True LVDS output buffers.
(6)eTX = Emulated-LVDS output buffers, either LVDS_E_3R or LVDS_E_1R.
(7)The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.
(8)These numbers represent the accumulated LVDS channels supported in ArriaIIGX row and column I/O banks.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 1:Overview for the Arria II Device FamilyArriaIIDevice Feature
Table1–3.Package Options and I/O Information for ArriaIIGZ Devices
780-Pin Flip Chip FBGA
29 mm x 29 mm
XCVRsDevice
I/O
EP2AGZ225EP2AGZ300EP2AGZ350
—281281
LVDS(6)—68 (RX or eTX) +
72 eTX68 (RX or eTX) +
72 eTX
I/O554554554
(Note1),(2), (3), (4), (5)
1517-Pin Flip Chip FBGA
40 mm x 40 mm
XCVRsI/O734734734
LVDS(7)179 (RX or eTX) + 184 (TX or eTX)179 (RX or eTX) + 184 (TX or eTX)179 (RX or eTX) + 184 (TX or eTX)
XCVRs242424
1152-Pin Flip Chip FBGA
35 mm x 35 mm
LVDS(7)135 (RX or eTX) + 140 (TX or eTX)135 (RX or eTX) + 140 (TX or eTX)135 (RX or eTX) + 140 (TX or eTX)
—1616
161616
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 1:Overview for the Arria II Device Family
Arria II Device Architecture
Arria II Device Architecture
Arria II devices include a customer-defined feature set optimized for cost-sensitive applications and offer a wide range of density, memory, embedded multiplier, I/O, and packaging options. Arria II devices support external memory interfaces and I/O protocols required by wireless, wireline, broadcast, computer, storage, and military markets. They inherit the 8-input ALM, M9K and M144K embedded RAM block, and high-performance DSP blocks from the Stratix? IV device family with a cost-optimized I/O cell and a transceiver optimized for 6.375Gbps speeds.
Figure1–1 and Figure1–2 show an overview of the Arria II GX and ArriaIIGZ device architecture, respectively.
Figure1–1.Architecture Overview for Arria II GX Devices
DLLPLLHigh-Speed Differential I/O,General Purpose I/O, andMemory InterfaceHigh-Speed Differential I/O,General Purpose I/O, andMemory InterfacePLLArria II GX FPGA Fabric(Logic Elements, DSP,Embedded Memory, Clock Networks)High-SpeedDifferential I/O with DPA,GeneralPurpose I/O, andMemoryInterfaceTransceiver BlocksAll the blocks in this graphic are for the largest density in theArria II GX family. The number of blocks can vary based on the density of the device.PLLPLLPlug and Play PCIe hard IP×××4, and ×8 1, 2, High-SpeedDifferential I/O with DPA,GeneralPurpose I/O, andMemoryInterfacePLLHigh-Speed Differential I/O,General Purpose I/O, andMemory InterfaceHigh-Speed Differential I/O,General Purpose I/O, andMemory InterfacePLLDLLArria II Device Handbook Volume 1: Device Interfaces and Integration
FPGA可编程逻辑器件芯片EP2AGX95EF29C4N中文规格书 - 图文
