Timings
Figure 17.Identification SequenceHost CommandCMDSTCONTENTCRCEZNID CyclesZP***PSTSMSxxxAF, SMSxxxFF, SMSxxxBF
CID or OCRCONTENTZZZai100466.1.2 Card Relative Address Timings
The SD Memory Card timings for CMD3 (SEND_RELATIVE_ADDR) are given in Figure18.The minimum delay between the host command and the card response is NCR clock cycles.
Figure 18.SEND_RELATIVE_ADDRESS CommandHost CommandCMDSTCONTENTCRCEZNCR CyclesZP***PSTResponseCONTENTCRCEZZZai100476.1.3 Data Transfer Mode
After publishing its RCA the card switches to the Data Transfer mode. The command is followed by two Z-bits (to leave time for the bus to switch direction) and then by P-bits pushed by the responding card as shown in Figure19. The timing diagram presented in Figure19 applies to all host commands followed by card responses, and to ACMD41 and CMD2 commands.
Figure 19.Response (Data Transfer Mode)Host CommandCMDSTCONTENTCRCEZNCR CyclesZP***PSTResponseCONTENTCRCEZZZai100476.1.4 Last Card Response, Next Host Command Timings
After receiving the last card response, the host can start the next command transmission after NRC clock cycles as shown in Figure20. The timing diagram presented in Figure20applies to any host command.
Figure 20.Response End To Next CMD Start (Data Transfer Mode)ResponseCMDSTCONTENTCRCEZNRC Cycles******ZSTHost CommandCONTENTCRCEai1004836/61 SMSxxxAF, SMSxxxFF, SMSxxxBFTimings
6.1.5 Last Host Command, Next Host Command Timings
The host can send a new command NCC clock cycles after sending the previous one as shown in Figure21.
Figure 21.Command Sequence (All Modes)Host CommandCMDSTCONTENTCRCEZNCC Cycles******ZSTHost CommandCONTENTCRCEai100496.2 Data Read
6.2.1
Single Block Read
The host selects one card for the data read operation by issuing CMD7, and sets the valid
block length for oriented data transfer by issuing CMD16. Figure22 shows the timings for a basing bus read operation. The sequence starts with a Single Block Read command
(CMD17) which specifies the start address in the argument field. The response is sent on the CMD line.
Data transmission from the card starts NAC after the end bit of the read command, where NAC is the access time. CRC check bits are appended to the data bits to allow the host to check for transmission errors.
Figure 22.Single Block Read CommandHost CommandCMDSTCONTENTCRCEZNCR CyclesZP***PSTResponseCONTENTCRCENAC CyclesDATZZZ****ZZZZZZP**********PSRead DataDDD***ai100506.2.2 Multiple Block Read
In Multiple Block Read mode, the card responds to the read command from the host by
sending a continuous flow of data blocks. The data flow is terminated by a
STOP_TRANSMISSION command (CMD12). Figure23 describes the Multiple Block Read command followed by the data blocks and Figure24, the response to a
STOP_TRANSMISSION command. The data transmission stops two clock cycles after the end bit of the STOP_TRANSMISSION command.
37/61Timings
Figure 23.Multiple Block Read CommandHost CommandCMDSTCONTENTNCRCyclesResponseCONTENTSMSxxxAF, SMSxxxFF, SMSxxxBF
CRCEZZP*PSTNAC CyclesCRCEZZPPPPPPPPPPPPPNAC CyclesCRCEP*******Read DataPSDDDDDai10051Read DataPSCONTENTDATZZZ****ZZZZZZP*******Figure 24.STOP_TRANSMISSION Command (CMD12, Data Transfer Mode) Host CommandCMDSTCONTENTCRCEZNCR CyclesZP* * *PSTResponseCONTENTCRCEDATDDD* * * * * * * * DDDEZZ* * * * * * * * * * * * * * * * * * * *ai100526.3 Data Write
6.3.1
Single Block Write
The host selects one card for the data write operation by issuing CMD7. The host sets the
valid block length for block oriented data transfer by issuing CMD16. Figure25 shows the timings of a basic bus write operation. The sequence starts with a Single Block Write command (CMD24) which determines (in the argument field) the start address. The card responds on the CMD line.
Data transfer from the host starts NWR clock cycles after the card response is received. CRC check bits are appended to the data sent by the host to allow the card to check for transmission errors. The card returns the CRC check result as a CRC status token on the DAT0 line. If a transmission error occurred, the card returns a negative CRC status ('101'). If the transmission completed successfully, the card returns a positive CRC status ('010') and starts programming the data.
If an error occurred while programming the Flash memory, the card ignores all further data blocks. In this case the card will not send any CRC response and so, there will be no CRC start bit on the bus and the three CRC status bits will read ('111').
Note that the CRC response is always output two clock cycles after the data.
If the card does not have any Data Receive buffer available, it indicates this condition by pulling the DAT0 data line to Low. It will stop pulling DAT0 to Low as soon as at least one Data Receive buffer for the defined data transfer block length becomes available. The level of DAT0 does not give any information about the data write status. The host can obtain this information by issuing a CMD13 (SEND_STATUS) to the card.
38/61 SMSxxxAF, SMSxxxFF, SMSxxxBFFigure 25.Block Write CommandHostCommandCMDNCRCard Response* * * * * * * * * * * * * * * * * *Write DataTimings
EZZP*PSTCONTENTCRCEZZPNWRPPPPPPPPCRC StatusBusyDAT0DAT1-DAT3ZZ* * * * * * *ZZZZZ* * * * * * *ZZZ* * ** * *ZZZZP * PSZZZZP * PSCONTENTCRCEZZSStatusESL * LEZCONTENTCRCEZZXXXXXXXXXZai100536.3.2 Multiple Block Write
In Multiple Block Write mode, the write command from the host is followed by a continuous
flow of data blocks from the host. The data flow is terminated by a STOP_TRANSMISSION command (CMD12).
As in the case of a Single Block Write operation, CRC check bits are appended to the data sent to allow the card to check for transmission errors. The card returns the CRC check result as a CRC status token on the DAT0 line.
If a transmission error occurred, the card returns a negative CRC status ('101'). If the transmission completed successfully, the card returns a positive CRC status ('010') and starts programming the data.
If an error occurred while programming the Flash memory, the card ignores all further data blocks. In this case the card will not send any CRC response and so, there will be no CRC start bit on the bus and the three CRC status bits will read ('111').
Figure26 describes a Multiple Block data transmission with and without a card busy signal.
Figure 26.Multiple Block Write CommandCardResponseCMDEZZPNWRDAT* * * * * * * * * * * * * * * * * *Write DataPPPPPNWR* * * * * * * * * * * * * * * * * *Write DataPPPPPPPPPBusyNWRCRC StatusCRC StatusZZP * PSData+CRCEZZSStatusEZP * PSData+CRCEZZSStatusESL * LEZP * Pai10056.4 STOP_TRANSMISSION Command
The STOP_TRANSMISSION command works in the same way as in the read mode.
Figure27 to Figure30 describe the timings of the STOP_TRANSMISSION command in different card states.
The card will consider that a data block was successfully received and is ready for
programming only if the CRC data of the block was validated and the CRC status token, returned to the host.
Figure28 is an example of an interrupted (by a STOP_TRANSMISSION command from the host) attempt to transmit the CRC status token. The result is the same as in other examples
39/61TimingsSMSxxxAF, SMSxxxFF, SMSxxxBF
where the STOP_TRANSMISSION command is implemented: the end bit of the
STOP_TRANSMISSION command from the host is followed, on the data line, by one more data bit, then an end bit and two Z-bits. The two Z-bits, which correspond to two clock cycles, are used to switch the bus direction. The received data block is considered incomplete and will not be programmed.
In the previous Stop Transmission examples, the host stopped the data transmission during an active data transfer.
In Figure29 and Figure30 the STOP_TRANSMISSION command is received by the card after all the data blocks have been sent.
In Figure29, the card is busy programming the last block when the STOP_TRANSMISSION command is received whereas in Figure30 the card is idle but the input buffers still contain data blocks to be programmed. In the second case, the card starts programming the blocks upon reception of the STOP_TRANSMISSION command and activates the busy signal.
Figure 27.STOP_TRANSMISSION During Data Transfer From The HostHost CommandCMDSTCONTENTCRCEZZPNCRCyclesP* * * * * * PSTCard ResponseCONTENTCRCEHost CommandSTCONTENTCard is programming DATDDDDDDDDDDEZZSL* * * * * * * * * * * * * * * * * * * * * *EZZZZZZZZai09518Figure 28.STOP_TRANSMISSION During CRC Status Transfer From CardHost CommandCMDSTCONTENTCRCEZZPDataBlockDATCRCStatus(1)NCRCyclesP * * * * * * PCard ResponseSTCONTENTCRCEHostCommandSTCONTENTCard is programming * * * * * * * * * * * * * * * * * * * * * *EZZZZZZZZai10062DDDDDZZSStatusEZZSL1.The card CRC status response was interrupted by the host.
Figure 29.STOP_TRANSMISSION Received After Last Data Block with Card Busy ProgrammingHost CommandNCRCyclesCard ResponseHostCommandSTCONTENTCMDSTCONTENTCRCEZZP* * *PSTCONTENTCRCECard is programming DATSL* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *LEZZZZZZZZai1006340/61
SD卡MiniSD卡与MicroSD卡的引脚定义等资料
