Periphery Performance
This section describes periphery performance, including high-speed I/O and external memory interface.
I/O performance supports several system interfacing, such as the LVDS high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. For
example, StratixIII devices I/O configured with voltage referenced I/O standards can achieve up to the stated system interfacing speed as indicated in “External Memory Interface Specifications” on page1–25. General-purpose I/O standards such as 3.3, 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 167 MHz and 1.2LVCMOS at 100MHz interfacing frequency with 10pF load.
1
Actual achievable frequency depends on design- and system-specific factors. You must perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Refer to the “Glossary” on page1–326 for the definitions of the high-speed timing specifications.
Table1–25 lists the true and emulated LVDS specifications for StratixIII devices.
Table1–25.True and Emulated LVDS Specifications for StratixIII Devices(Note1), (2)(Part 1 of 3)
Symbol
fHSCLK_in
(input clock
frequency)—True Differential I/O Standards
MaxMaxMaxClock boost
factor W = 1 to 40 (3)
5—8005—7175—7175—717
MaxMinMinMinMinTypTypTypTypConditions
MHz
fHSCLK_in
(input clock Clock boost
frequency)—Single factor W = 1 to 40 Ended I/O (3)Standards (9)fHSCLK_out
(output clockfrequency)Transmitter
5—8005—7175—7175—717MHz
—5—800 (7)5—717 (7)5—717 (7)5—717 (7)MHz
SERDES factor J = 3 to 10 (8)SERDES factorJ = 2, Uses DDR RegisterSERDES factorJ = 1, Uses SDR Register
LVDS_E_3R -fHSDR (data rate)
(4)(4)
——
1600(4)
(4)(4)
——
1250(4)
(4)(4)
——
1250(4)
(4)(4)
——
1250(4)
MbpsMbps
fHSDR (data rate)
(4)(4)
——
(4)1100
(4)(4)
——
(4)1100
(4)(4)
——
(4)800
(4)(4)
——
(4)800
MbpsMbps
SERDES factorJ = 4 to 10
Stratix III Device Handbook, Volume 2
UnitC2C3, I3C4, I4C4L, I4L
Chapter 1:StratixIII Device Datasheet: DC and Switching CharacteristicsSwitching Characteristics
Figure1–3 shows the LVDS Soft-CDR/ DPA sinusoidal jitter tolerance specifications for StratixIII devices.
Figure1–3.LVDS Soft-CDR/DPA Sinusiodal Jitter Tolerance Specification for StratixIII Devices
Table1–27 lists the LVDS Soft-CDR/ DPA sinusiodal jitter mask values for StratixIII devices.
Table1–27.LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for StratixIII Devices
Jitter Frequency (Hz)
F1F2F3F4
10,00017,5651,493,00050,000,000
Jitter Amplitude
25.00025.0000.3500.350
UnitUIUIUIUI
External Memory Interface Specifications
The following sections describe the external memory I/O timing specifications and the DLL and DQS block specifications.
f
For more information about the maximum clock rate support for external memory interfaces with a half-rate or full-rate controller, refer to SectionIII: System Performance Specifications of the External Memory Interfaces Handbook.External Memory I/O Timing Specifications
Table1–28 and Table1–29 list StratixIII device timing uncertainties on the read and write data paths. Use these specifications to determine timing margins for source synchronous paths between the StratixIII FPGA and the external memory device. For more information, refer to the figure for “SW (sampling window)” in the “Glossary” on page1–326.
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Datasheet: DC and Switching Characteristics
I/O Timing
OCT Calibration Block Specifications
Table1–34 lists the on-chip termination calibration block specifications for StratixIII devices.
Table1–34.On-Chip Termination Calibration Block Specification
SymbolOCTUSRCLKtOCTCALtOCTSHIFTtRS_RT
Description
Clock required by OCT calibration blocks Number of OCTUSRCLK clock cycles required for OCT Rs and Rt calibration
Number of OCTUSRCLK clock cycles required for OCT code to shift out per OCT calibration blockTime required to dynamically switch from Rs to Rt
Min————
Typical—1000282.5
Max20———
UnitMHzcyclescyclesns
DCD Specifications
Table1–35 lists the worst case duty cycle distortion for StratixIII devices. Table1–35.Duty Cycle Distortion on StratixIII I/O Pins(Note1)
Symbol
Min
Output Duty Cycle
Note to Table1–35:
(1)The DCD specification applies to clock outputs from the PLLs, global clock tree, and IOE driving dedicated and
general-purpose I/O pins.
C2Max55
Min45
C3Max55
Min45
C4Max55
Unit%
45
I/O Timing
The following sections describe the timing models, preliminary and final timings, I/O timing measurement methodology, I/O default capacitive loading, programmable IOE delay, programmable output buffer delay, user I/O timing, and dedicated clock pin timing.
Timing Model
The DirectDrive technology and MultiTrack interconnect ensure predictable
performance, accurate simulation, and accurate timing analysis across all StratixIII device densities and speed grades. This section describes the performance of the StratixIII device I/Os.
All specifications except the fast model are representative of worst-case supply voltage and junction temperature conditions. Fast model specifications are representative of best case process, supply voltage, and junction temperature conditions.
The timing numbers listed in this section are extracted from the QuartusII software version 8.1.
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Datasheet: DC and Switching CharacteristicsI/O Timing
Preliminary and Final Timing
Timing models can have either preliminary or final status. The QuartusII software issues an informational message during design compilation if the timing models are preliminary. Table1–36 lists the status of the StratixIII device timing models.Preliminary status means that the timing models are subject to change in future QuartusII releases. Initially, timing numbers are created using simulation results, process data, and other known parameters. Parts of the timing models may be correlated to silicon measurements. Various tests are used to make the preliminary numbers as close to the actual timing parameters as possible.
Final timing models are based on simulation models that are characterized versus the actual device measurements under all allowable operating conditions. When the timing models are final, all or most of the StratixIII family devices have been
completely characterized and no further changes to the timing model are expected.Table1–36.Timing Model Status for StratixIII Devices
Device
EP3SL50EP3SL70EP3SL110EP3SL150EP3SL200EP3SL340EP3SE50EP3SE80EP3SE110EP3SE260
Preliminary
——————————
Finalvvvvvvvvvv
I/O Timing Measurement Methodology
Altera characterizes timing delays at the worst-case process, minimum voltage, and maximum temperature for input register setup time (tsu) and hold time (th). The
QuartusII software uses the following equations to calculate tsu and th timing for the StratixIII devices input signals.tsu =
+data delay from the input pin to the input register+micro setup time of the input register
-clock delay from the input pin to the input registerth =
-data delay from the input pin to the input register+micro hold time of the input register
+clock delay from the input pin to the input register
Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S20B672C7中文规格书 - 图文
