SII51003-4.2
IEEE Std. 1149.1 JTAG Boundary-Scan Support
All Stratix?II devices provide Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry that complies with the IEEE
Std.1149.1. JTAG boundary-scan testing can be performed either before or after, but not during configuration. StratixII devices can also use the JTAG port for configuration with the Quartus?II software or hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc).
StratixII devices support IOE I/O standard setting reconfiguration through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user mode through the CONFIG_IO instruction. You can use this capability for JTAG testing before configuration when some of the StratixII pins drive or receive from other devices on the board using voltage-referenced standards. Because the StratixII device may not be configured before JTAG testing, the I/O pins may not be configured for appropriate
electrical standards for chip-to-chip communication. Programming those I/O standards via JTAG allows you to fully test I/O connections to other devices.
A device operating in JTAG mode uses four required pins, TDI,TDO, TMS, and TCK, and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the TDI,TMS and TRST pins have weak internal pull-ups. The JTAG input pins are powered by the 3.3-V VCCPD pins. The TDO output pin is powered by the VCCIO power supply of bank 4.StratixII devices also use the JTAG port to monitor the logic operation of the device with the SignalTap?II embedded logic analyzer. StratixII devices support the JTAG instructions shown in Table3–1.1
StratixII, Stratix, Cyclone?II, and Cyclone devices must be within the first 17 devices in a JTAG chain. All of these devices have the same JTAG controller. If any of the StratixII, Stratix, CycloneII, or Cyclone devices are in the 18th of further position, they fail configuration. This does not affect SignalTapII.
The StratixII device instruction register length is 10 bits and the USERCODE register length is 32 bits. Tables3–2 and 3–3 show the boundary-scan register length and device IDCODE information for StratixII devices.
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Table3–1.StratixII JTAG InstructionsJTAG Instruction
SAMPLE/PRELOAD
Instruction Code
00 0000 0101
Description
Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap II embedded logic analyzer.
Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation.Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO.
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register.
Used when configuring a StratixII device via the JTAG port with a USB Blaster, MasterBlaster?, ByteBlasterMV?, or ByteBlaster II download cable, or when using a .jam or .jbc via an embedded processor or JRunner.
EXTEST(1)00 0000 1111
BYPASS11 1111 1111
USERCODE00 0000 0111
IDCODEHIGHZ (1)
00 0000 011000 0000 1011
CLAMP (1)00 0000 1010
ICR instructions
PULSE_NCONFIGCONFIG_IO (2)
00 0000 000100 0000 1101
Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for JTAG testing. Can be executed before, during, or after
configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction holds nSTATUS low to reset the configuration device. nSTATUS is held low until the IOE configuration register is loaded and the TAP controller state machine transitions to the UPDATE_DR state.
Monitors internal device operation with the SignalTap II embedded logic analyzer.
SignalTap II instructionsNotes to Table3–1:(1)(2)
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.For more information on using the CONFIG_IO instruction, see the MorphIO: An I/O Reconfiguration Solution for Altera Devices White Paper.
Stratix II Device Handbook, Volume 1
Configuration & Testing
The QuartusII software has an Auto Usercode feature where you can choose to use the checksum value of a programming file as the JTAG user code. If selected, the checksum is automatically loaded to the USERCODE register. Turn on the Auto Usercode option by clicking Device & Pin Options, then General, in the Settings dialog box (Assignments menu).Table3–2.StratixII Boundary-Scan Register Length
Device
EP2S15EP2S30EP2S60EP2S90EP2S130EP2S180
Boundary-Scan Register Length
1,1401,6922,1962,7483,4203,948
Table3–3.32-Bit StratixII Device IDCODE
IDCODE (32 Bits) (1)
Device
EP2S15EP2S30EP2S60EP2S90EP2S130EP2S180Notes to Table3–3:(1)(2)
The most significant bit (MSB) is on the left.
The IDCODE's least significant bit (LSB) is always 1.
Version (4Bits)
000000000001000000000000
Part Number (16 Bits)
0010 0000 1001 00010010 0000 1001 00100010 0000 1001 00110010 0000 1001 01000010 0000 1001 01010010 0000 1001 0110
Manufacturer Identity (11
LSB (1Bit) (2)
Bits)
000 0110 1110000 0110 1110000 0110 1110000 0110 1110000 0110 1110000 0110 1110
111111
1
Stratix, StratixII, Cyclone, and CycloneII devices must be
within the first 17 devices in a JTAG chain. All of these devices have the same JTAG controller. If any of the Stratix, StratixII, Cyclone, and CycloneII devices are in the 18th or after they fail configuration. This does not affect SignalTapII.
Stratix II Device Handbook, Volume 1
Configuration
Table3–5.StratixII Configuration Features(Part 2 of2)Configuration Scheme
PPAJTAG
Configuration Method
MAX II device or microprocessor and flash deviceDownload cable (4)
MAX II device or microprocessor and flash device
Design SecurityDecompression
Remote System Upgrade
v
Notes for Table3–5:(1)(2)(3)(4)
In these modes, the host system must send a DCLK that is 4× the data rate.
The enhanced configuration device decompression feature is available, while the StratixII decompression feature is not available.
Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported.
The supported download cables include the Altera USB Blaster universal serial bus (USB) port download cable, MasterBlaster serial/USB communications cable, ByteBlasterII parallel port download cable, and the ByteBlasterMV parallel port download cable.
f
See the Configuring StratixII & StratixIIGX Devices chapter in volume2 of the StratixII Device Handbook or the StratixIIGX Device Handbook for more information about configuration schemes in StratixII and StratixIIGX devices.
Device Security Using Configuration Bitstream Encryption
StratixII FPGAs are the industry’s first FPGAs with the ability to decrypt a configuration bitstream using the Advanced Encryption Standard (AES) algorithm. When using the design security feature, a 128-bit
security key is stored in the StratixII FPGA. To successfully configure a StratixII FPGA that has the design security feature enabled, it must be configured with a configuration file that was encrypted using the same 128-bit security key. The security key can be stored in non-volatile
memory inside the StratixII device. This non-volatile memory does notrequire any external devices, such as a battery back-up, for storage.
Stratix II Device Handbook, Volume 1
Configuration & Testing
1
An encryption configuration file is the same size as a non-encryption configuration file. When using a serial configuration scheme such as passive serial (PS) or active serial (AS), configuration time is the same whether or not the design security feature is enabled. If the fast passive parallel (FPP) scheme us used with the design security or decompression feature, a 4× DCLK is required. This results in a slower
configuration time when compared to the configuration time of an FPGA that has neither the design security, nor
Stratix II Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP1S25F780C7L中文规格书 - 图文
