Chapter 2: XPHY Architecture
XPLL placement in the following figure is representative, the XPLL locations varies (with respectto nibbles).
Figure 4: Inter-nibble and Inter-byte Clocking Within an XPIO Bank
Inter-nibble clocking MUXFIFO_WR_CLKFIFO_WR_CLKFIFO_WR_CLKFIFO_WR_CLKFIFO_WR_CLKFIFO_WR_CLKFIFO_WR_CLKFIFO_WR_CLKFIFO_WR_CLKXPHY 0XPHY 1XPHY 2XPHY 3XPHY 8XPHY 4XPHY 5XPHY 6XPHY 7XPLLXPLLXCC/GCXCC/GCXCC/GCXCC/GCXCCXCCXCCXCCInter-byte clocking MUXONLY GCs can route to PLLsX21607-102319AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual
XCCChapter 2: XPHY Architecture
Figure 4 has been translated into a table, as follows.
Table 6: Inter-byte and Inter-nibble Clocking in an XPIO Bank
XPHYNibble
012345678
Can Route To (Through Inter-byte,
Can Route To (ThroughCan Route To (Through
Inter-nibble, or a Combination of the
Inter-nibble Clocking)Inter-byte Clocking)
Two)
10325476---0, 41, 52, 63, 78--10
0, 1, 3, 4, 5, 6, 7, 80, 1, 2, 4, 5, 6, 70, 1, 2, 3, 5, 6, 7, 80, 1, 2, 3, 4, 6, 7
7, 86-
As shown in the clocking figures, within a bank there are two types of clock inputs that serve twodifferent purposes:
?Global Clock (GC): Clock input with dedicated clock routing designed to have low skew, lowduty cycle distortion, and improved jitter resistance. As such, it is recommended for externalclocks to enter through GC pins. For interfaces that use XPHY, the GC pins are typically usedas the clock source for the XPLLs, which in turn clock the XPHY. GCs can reach all XPLLs in anXPIO bank as well as XPLLs in the adjacent banks.?XCC: Strobe input for XPHY receive interfaces
?Both GC and XCC: These pins can act as GCs and/or XCCs
Note: If a GC, XCC, or GC/XCC input is not used to receive a clock or strobe, it can be used as a regular I/Opin.
Refer to Versal ACAP Clocking Resources Architecture Manual (AM003) for a more detailedexplanation of GC and XCC pins.
The following figure shows the XCC and GC pins that can accept a clock and the NIBBLESLICEswith which they are associated. Clocks entering on GC or XCC inputs (as opposed to data
entering on those pins), regardless of whether single-ended or differential, must enter the I/O pinassociated with NIBBLESLICE[0]. If the clock is differential, the complementary side of the clock(incoming on the I/O pin associated with NIBBLESLICE[1]) should be connected to the samedifferential buffer as the signal incoming to the I/O pin of NIBBLESLICE[0]. Because
NIBBLESLICE[0] is the only NIBBLESLICE that is capable of connecting to the strobe circuitry,
AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual
FPGA可编程逻辑器件芯片XC2V1000-6BF957C中文规格书
