10.Hot Socketing and Power-On Reset in
StratixIII Devices
SIII51010-1.7
This chapter describes information about hot-socketing specifications, power-on reset (POR) requirements, and their implementation in Stratix?III devices.
StratixIII devices offer hot socketing, also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. You can insert or remove a StratixIII device or a board in a system during system operation without causing undesirable effects to the running system bus or board that is inserted into the system.
The hot socketing feature also removes some of the difficulty when you use StratixIII devices on PCBs that contain a mixture of 3.3-, 3.0-, 2.5-, 1.8-, 1.5-, and 1.2-V devices. With the StratixIII hot socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board.The StratixIII hot-socketing feature provides:
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Board or device insertion and removal without external components or boardmanipulation
Support for any power-up sequence
I/O buffers non-intrusive to system buses during hot insertion
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This section also describes the POR circuitry in StratixIII devices. POR circuitry keeps the devices in the reset state until the power supplies are within operating range.
StratixIII Hot-Socketing Specifications
StratixIII devices are hot-socketing compliant without the need for external components or special design requirements. Hot socketing support in StratixIII devices has the following advantages:
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You can drive the device before power-up without damaging it.
I/O pins remain tri-stated during power-up. The device does not drive out beforeor during power-up, thereby not affecting other buses in operation.
You can insert a StratixIII device into or remove it from a powered-up systemboard without damaging or interfering with normal system/board operation.
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StratixIII Devices Can Be Driven Before Power Up
You can drive signals into I/O pins, dedicated input pins, and dedicated clock pins of StratixIII devices before or during power up or power down without damaging the device. StratixIII devices support power up or power down of the power supplies in any sequence in order to simplify system-level design.
Stratix III Device Handbook, Volume 1
Chapter 10:Hot Socketing and Power-On Reset in StratixIII Devices
Chapter Revision History
Stratix III Device Handbook, Volume 1
Chapter 11:Configuring StratixIII Devices
Fast Active Serial Configuration (Serial Configuration Devices)
Programming Serial Configuration Devices
Serial configuration devices are non-volatile, flash-memory-based devices. You can program these devices in-system using the USB-Blaster? or ByteBlaster?II
download cable. Alternatively, you can program them using the Altera programming unit (APU), supported third-party programmers, or a microprocessor with the SRunner software driver.
You can perform in-system programming of serial configuration devices by using the conventional AS programming interface or JTAG interface solution.
Because serial configuration devices do not support the JTAG interface, the
conventional method to program them is by using the AS programming interface. The configuration data used to program serial configuration devices is downloaded by using the programming hardware.
During in-system programming, the download cable disables device access to the AS interface by driving the nCE pin high. StratixIII devices are also held in reset by a low level on nCONFIG. After programming is complete, the download cable releases nCE and nCONFIG, allowing the pull-down and pull-up resistors to drive GND and
VCCPGM, respectively. Figure11–12 shows the download cable connections to the serial configuration device.
Altera has developed the Serial FlashLoader (SFL), which is an in-system
programming solution for serial configuration devices using the JTAG interface. This solution requires the StratixIII device to be a bridge between the JTAG interface and the serial configuration device.
Stratix III Device Handbook, Volume 1
Chapter 12:Remote System Upgrades with StratixIII DevicesRemote System Upgrade Mode
Remote System Upgrade Mode
Remote system upgrade has one mode of operation: remote update mode. The remote update mode allows you to determine the functionality of your system upon power-up and offers different features.
In remote update mode, StratixIII devices load the factory configuration image upon power up. The user-defined factory configuration determines which application configuration is to be loaded and triggers a reconfiguration cycle. The factory configuration may also contain application logics.
When used with serial configuration devices, the remote update mode allows an application configuration to start at any flash sector boundary. This translates to a maximum of 128 pages in the EPCS64 device and 32pages in the EPCS16 device, where the minimum size of each page is 512 KBits. Additionally, the remote update mode features a user watchdog timer that determines the validity of an application configuration.
Remote Update Mode
When a StratixIII device is first powered-up in remote update mode, it loads the factory configuration located at page zero (page registers PGM[23:0] = 24'b0). You should always store the factory configuration image for your system at page address zero. This corresponds to the start address location 0×000000 in the serial configuration device.
The factory configuration image is user-designed and contains soft logic to do the following:
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Process any errors based on status information from the dedicated remote systemupgrade circuitry
Communicate with the remote host and receive new application configurationsand store this new configuration data in the local non-volatile memory deviceDetermine which application configuration is to be loaded into the StratixIIIdevice
Enable or disable the user watchdog timer and load its time-out value (optional)Instruct the dedicated remote system upgrade circuitry to initiate areconfiguration cycle
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Figure12–4 shows the transitions between the factory and application configurations in remote update mode.
Stratix III Device Handbook, Volume 1
Chapter 12:Remote System Upgrades with StratixIII Devices
Remote System Upgrade Mode
Figure12–4.Transitions Between Configurations in Remote Update Mode
Configuration ErrorPower UpSet Control Register and ReconfigureApplication 1 ConfigurationConfigurationError
Factory Configuration(page 0)Reload a Different ApplicationReload a Different ApplicationSet Control Register and ReconfigureApplication nConfigurationConfiguration ErrorAfter power up or a configuration error, the factory configuration logic is loaded automatically. The factory configuration also needs to specify whether to enable the user watchdog timer for the application configuration and if enabled, to include the timer setting information as well.
The user watchdog timer ensures that the application configuration is valid and functional. The timer must be continually reset within a specific amount of time during user mode operation of an application configuration. Only valid application configurations contain the logic to reset the timer in user mode. This timer reset logic should be part of a user-designed hardware and/or software health monitoring signal that indicates error-free system operation. If the timer is not reset in a specific amount of time, for example, the user application configuration detects a functional problem or if the system hangs, the dedicated circuitry updates the remote system upgrade status register, triggering the loading of the factory configuration.1
The user watchdog timer is automatically disabled for factory configurations. For more information about the user watchdog timer, refer to “User Watchdog Timer” on page12–11.
If there is an error while loading the application configuration, the cause of the reconfiguration is written by the dedicated circuitry to the remote system upgrade status register. Actions that cause the remote system upgrade status register to be written:
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nSTATUS driven low externallyInternal CRC error
User watchdog timer time out
Stratix III Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP2S30F672I5中文规格书 - 图文
