Table4–19.Stratix II GX Transceiver Block AC Specification Notes(1), (2), (3)(Part 19 of19)
-3 Speed
Commercial Speed
GradeMin
Notes to Table4–19:(1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)
Dedicated REFCLK pins were used to drive the input reference clocks.Jitter numbers specified are valid for the stated conditions only.
Refer to the protocol characterization documents for detailed information.
HiGig configuration is available in a -3 speed grade only. For more information, refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook.
Stratix II GX transceivers meet CEI jitter generation specification of 0.3 UI for a VOD range of 400mV to 1000 mV. The Sinusoidal Jitter Tolerance Mask is defined only for low voltage (LV) variant of CPRI.The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.The jitter numbers for CPRI are compliant to the CPRI Specification V2.1.
The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
The Fibre Channel transmitter jitter generation numbers are compliant to the specification at βT interoperability point.The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at βR interoperability point.
Symbol/Description
Conditions
-4 SpeedCommercial and Industrial Speed
GradeMin
Typ
Max
-5 Speed
Commercial Speed
GradeMin
Typ
Max
Unit
TypMax
Table4–20 provides information on recommended input clock jitter for each mode.
Table4–20.Recommended Input Clock Jitter(Part 1 of2)Mode
PCI-E(OIF) CEI PHYGIGEXAUI
Reference Clock (MHz)
100156.25622.0862.5125156.25
Vectron LVPECL XOType/Model
VCC6-Q/RVCC6-Q/RVCC6-QVCC6-Q/RVCC6-Q/RVCC6-Q/R
RMS Jitter Period Jitter
Frequency
(12 kHz to 20 (Peak to
Range (MHz)
MHz) (ps)Peak) (ps)
10 to 27010 to 270270 to 80010 to 27010 to 27010 to 270
0.30.320.30.30.3
232330232323
Phase Noise
at 1 MHz(dB c/Hz)
-149.9957-146.2169Not available-149.9957-146.9957-146.2169
Stratix II GX Device Handbook, Volume 1
DC and Switching Characteristics
Stratix II GX Device Handbook, Volume 1
DC and Switching Characteristics
Table4–29. 2.5-V LVDS I/O SpecificationsSymbol
VCCIO
Parameter
I/O supply voltage for left and right I/O banks (1, 2, 5, and 6)Input differential voltage swing (single-ended)Input common mode voltageOutput differential voltage (single-ended)Output common mode voltage
Receiver differential input discrete resistor (external to StratixIIGX devices)
ConditionsMinimum
2.375
Typical
2.5
Maximum
2.625
Unit
V
VIDVICMVODVOCMRL
100200
RL = 100 ΩRL = 100 Ω
2501.12590
3501,250
9001,8004501.375
mVmVmVVΩ
100110
Table4–30.3.3-V LVDS I/O SpecificationsSymbol
VCCIO (1)
Parameter
I/O supply voltage for top and bottom PLL banks (9, 10, 11, and 12)
Input differential voltage swing (single-ended)Input common mode voltageOutput differential voltage (single-ended)Output common mode voltage
Receiver differential input discrete resistor (external to StratixIIGX devices)
ConditionsMinimum
3.135
Typical
3.3
Maximum
3.465
Unit
V
VIDVICMVODVOCMRL
100200
RL = 100 ΩRL = 100 Ω
25084090
3501,250
9001,8007101,570
mVmVmVmVΩ
100110
Note to Table4–30:(1)
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO. The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table4–31.PCML SpecificationsNote(1)Symbol
Reference Clock3.3-V PCML1.5-V PCML1.2-V PCMLVID VICMRReceiver3.3-V PCML1.5-V PCML1.2-V PCMLVID VICMR
Transmitter1.5-V PCML1.2-V PCMLVCCHVOD
Transmitter supported PCML standards
Output buffer supply voltagePeak-to-peak differential output voltage
The specifications are located in Table4–5 on page4–4.The specifications are located in Tables4–7, 4–8, 4–9, 4–10, 4–11, and 4–12.
The specifications listed in these tables are applicable to PCML output standards.
VOCMR
Output common mode voltageOn-chip termination resistors
The specifications are located in the Transmitter section of Table4–6 on page4–4.
The specifications listed in Table4–6 are applicable to PCML output standards.
Note to Table4–31:(1)
StratixII GX devices support PCML input and output on GXB banks 13, 14, 15, 16, and 17. This table references StratixII GX PCML specifications that are located in other sections of the StratixII GX Device Handbook.
Parameter
Reference clock supported PCML standards
Peak-to-peak differential input voltage
Input common mode voltageOn-chip termination resistors
References
The specifications are located in the Reference Clock section of Table4–6 on page4–4.
The specifications listed in Table4–6 are applicable to PCML input standards.
Receiver supported PCML standards
Peak-to-peak differential input voltage
Input common mode voltageOn-chip termination resistors
The specifications are located in the Receiver section of Table4–6 on page4–4.
The specifications listed in Table4–6 are applicable to PCML input standards.
Stratix II GX Device Handbook, Volume 1
Power
Consumption
f
Timing Model
DC and Switching Characteristics
Altera offers two ways to calculate power for a design: the Excel-based PowerPlay early power estimator power calculator and the Quartus? II PowerPlay power analyzer feature.
The interactive Excel-based PowerPlay early power estimator is typically used prior to designing the FPGA in order to get an estimate of device power. The QuartusII PowerPlay power analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The power analyzer can apply a combination of user-entered, simulation-derived and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates.In both cases, these calculations should only be used as an estimation of power, not as a specification.
For more information on PowerPlay tools, refer to the PowerPlay Early Power Estimators (EPE) and Power Analyzer, the Quartus II PowerPlay Analysis and Optimization Technology, and the PowerPlay Power Analyzer chapter in volume 3 of the QuartusII Handbook. The PowerPlay early power estimators are available on the Altera web site at www.altera. com.1
See Table4–23 on page42 for typical ICC standby specifications.
The DirectDrive technology and MultiTrack interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all StratixIIGX device densities and speed grades. This section describes and specifies the performance, internal, external, and PLL timing specifications.
All specifications are representative of worst-case supply voltage and junction temperature conditions.
Preliminary and Final Timing
Timing models can have either preliminary or final status. The QuartusII software issues an informational message during the design compilation if the timing models are preliminary. Table4–52 shows the status of the StratixIIGX device timing models.
Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible.
Stratix II GX Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP1S25F672C-7N中文规格书 - 图文
