Chapter7
GTX Receiver (RX)
This chapter shows how to configure and use each of the functional blocks inside the GTX receiver.
Receiver Overview
Each GTX transceiver includes an independent receiver, made up of a PCS and a PMA. Figure7-1 shows the functional blocks of the receiver (RX). High-speed serial data flows from traces on the board into the PMA of the RX, into the PCS, and finally into the FPGA logic. Refer to AppendixE, “Low Latency Design,” for latency information on this block diagram.
X-Ref Target - Figure 7-1124RXCDRSIPORXDFEQERXOOB6Over-samplingRXPolarity7CommaDetectandAlign161110B/8BDecoder12ElasticBufferRXGearbox3SharedPMAPLLDivider5915Loss of SyncPRBSCheckFPGARXInterface10RX Status ControlFrom Shared PMA PLLRX-PMARX-PCS81314UG198_c7_01_050207Figure 7-1:GTX RX Block Diagram
The key elements within the GTX receiver are:1.2.3.4.5.6.7.8.9.
“RX Termination and Equalization,” page 162“Decision Feedback Equalization,” page 166“RX OOB/Beacon Signaling,” page 173“RX Clock Data Recovery,” page 179“Serial In to Parallel Out,” page 183“Oversampling,” page 185“RX Polarity Control,” page 189“PRBS Detection,” page 190
“Configurable Comma Alignment and Detection,” page 191
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Decision Feedback Equalization
Figure7-4 illustrates a conceptual view of the DFE.
X-Ref Target - Figure 7-4PLimiterNDFETo CDRDFETAP1MONITOR[4:0]DFECLKDFEEYEDACMONITOR[4:0]–TAP1DFETAP1[4:0]DFETAP2MONITOR[4:0]DFECLK–TAP2DFETAP2[4:0]AutomaticTAPValueControlDFE_CFG[9:0]DFEControllerRX Serial Clock–TAP4DFETAP4[3:0]UG198_c7_04_071508TDFETAP1MONITOR[4:0]TDFETAP2MONITOR[4:0]DFETAP3MONITOR[3:0]DFE CLKDFECLK–TAP3DFETAP3[3:0]DFETAP4MONITOR[3:0]DFECLKTDFETAP3MONITOR[3:0]TDFETAP4MONITOR[3:0]Figure 7-4:DFE Conceptual View
The DFE allows better compensation of transmission channel losses by providing a closer adjustment of filter parameters than when using a linear equalizer. However, a DFE cannot remove the pre-cursor of a transmitted bit. A linear equalizer allows pre-cursor and post-cursor attenuation, but has only a coarse adaptor to the transmission channel
characteristic. The GTX_DUAL DFE in the GTX RX is a time-discrete adaptive high-pass filter(1). The TAP values of the DFE are the coefficients of this filter that are set by the automatic TAP value controller. The optimization criteria for the TAP values and the DFECLK delay is the vertical eye opening. The DFE_CFG_(0/1) attribute switches off auto-calibration and overrides the TAP values and the DFECLK delay.
Channel BER Optimization Approach
The TX pre-emphasis, the RX equalization, and the DFE work together to optimize the BER for a channel. In general, the steps for optimizing the BER are:1.
Determining adequate transmitter swing.
1.Refer to Digital Filters - Basics and Design, page95ff [Ref10] for a block diagram of an IIR filter. The DFE can be seen as an IIR filter with only a recursive part, which implies that the coefficients for the non-recursive partare all equal to zero with the exception of b0, which is one.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
RX OOB/Beacon Signaling
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 7:GTX Receiver (RX)
Table 7-15:Example Clock Generation Settings for SATAParameter
Example 1
2512520
Example 2
75237.513.33333333
Example 3
10042520
Example 4
15062520
Example 5
250102520
Example 6
300122520
CLKIN (MHz)OOB_CLK_DIVIDERSquelch Clock (MHz)Effective Sample Period (ns)
Table7-16 shows all the minimum and maximum values defined in SATA for burst and idle lengths, along with example calculations based on the squelch clock frequencies computed in Table7-15.
Table 7-16:
Example SATA Attribute Settings
Parameter
Shortest burst width that must be rejectedMinBurstWidth
Shortest burst width that must be acceptedNominal burst length
Longest burst width that must be acceptedMaxBurstWidth
Longest burst width that must be rejectedShortest idle width that must be rejected for COMINITMinInitWidth
Shortest idle width that must be accepted for COMINIT
Nominal idle width for COMINIT
Longest idle width that must be accepted for COMINITMaxInitWidth
Longest idle width that must be rejected for COMINIT
Shortest idle width that must be rejected for COMWAKEMinWakeWidth
Shortest idle width that must be accepted for COMWAKE
Nominal idle width for COMWAKE
Longest idle width that must be accepted for COMWAKEMaxWakeWidth
Longest idle width that must be rejected for COMWAKE
175101.3106.711252555304320336175175101107112ns55
CyclesCyclesCyclesCyclesCycles2.845.15.35.678.88.81215.216.016.82226.32.845.15.35.678.8
4.167.68.08.41113.113.11822.824.025.23239.44.167.68.08.41113.1
2.845.15.35.678.88.81215.216.016.82226.32.845.15.35.678.8
2.845.15.35.678.88.81215.216.016.82226.32.845.15.35.678.8
2.845.15.35.678.88.81215.216.016.82226.32.845.15.35.678.8
Cycles2.357142857
34.3414285714.572857143
4.867.57.51013.0285714313.71428571
14.41822.52.357142857
34.3414285714.572857143
4.867.5
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
RX Clock Data Recovery
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC2S150-5FGG456I中文规格书 - 图文
