SIII52001-2.1
Electrical Characteristics
Operating Conditions
When Stratix?III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of StratixIII devices, system designers must consider the operating requirements discussed in this chapter. StratixIII devices are offered in both
commercial and industrial grades. Commercial devices are offered in –2 (fastest), –3, –4 and –4L speed grades. Industrial devices are offered only in –3, –4, and –4L speedgrades.
1
In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with “C” prefix and industrial with “I” prefix.
Commercial devices are therefore indicated as C2, C3, C4, and C4L per respective speed grades. Industrial devices are indicated as I3, I4, and I4L.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for StratixIII devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied at these conditions. Conditions beyond those listed in Table1–1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods may have adverse effects on the device.
Table1–1.StratixIII Device Absolute Maximum Ratings (Note1)(Part 1 of 2)
SymbolVCCLVCCVCCD_PLLVCCA_PLLVCCPTVCCPGMVCCPDVCCIOVCC_CLKINVCCBATVI
Parameter
Selectable core voltage power supplyI/O registers power supplyPLL digital power supplyPLL analog power supply
Programmable power technology power supplyConfiguration pins power supplyI/O pre-driver power supplyI/O power supply
Differential clock input power supply (top and bottom I/O banks only)
Battery back-up power supply for design security volatile key registerDC Input voltage
Minimum-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5
Maximum1.651.651.653.753.753.93.93.93.753.754.0
UnitVVVVVVVVVVV
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table1–30.Sampling Window (SW) - Read Side (Note1) (Part 2 of 2)
C2
Memory Type
I/O Standard
Width
VCCL = 1.1VSW (ps)Setup
QDRII/II+ SRAMQDRII/II+ SRAM Emulation (2) RLDRAM IIRLDRAM II
Notes to Table1–30:.
(1)The values apply to Column I/Os, Row I/Os and Hybrid mode interface. Column I/Os refer to Top and Bottom I/Os. Hybrid mode refers to DQ/DQS groups
wrapping over Column I/Os and Row I/Os of the device.(2)Please refer to the section “Supporting ×36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packages” on page8–20 in chapter 8 External Memory
Interface in StratixIII Devices for the implementation.
C3, I3VCCL = 1.1VSW (ps)Setup314314264264
Hold291337356356
C4, I4VCCL = 1.1VSW (ps)Setup337337287287
Hold291350356356
C4L, I4LVCCL = 1.1VSW (ps)Setup337337287287
Hold291350356356
C4L, I4LVCCL = 0.9VSW (ps)Setup337337287287
Hold291350356356
Hold286328336336
1.8 V HSTL1.8 V HSTL1.5 V HSTL1.8 V HSTL
×9, ×18, ×36×36×9, ×18×9, ×18
261261211211
Table1–31.Transmitter Channel-to-Channel Skew (TCCS) - Write Side (Note1)(Part 1 of 2)
C2
Memory Type
I/O Standard
Width
VCCL = 1.1VTCCS (ps)Lead
DDR3 SDRAM (with Deskew circuitry, 401MHz–533MHz)DDR3 SDRAM(8-tap phase offset, 375MHz-400MHz)
DDR3 SDRAM (8-tap phase offset, 360MHz-375MHz)
DDR3 SDRAM(10-tap phase offset, 333MHz-360MHz)
DDR3 SDRAM(10-tap phase offset, 300MHz-333MHz)
DDR2 SDRAM Differential DQS
DDR2 SDRAM Single-ended DQS
1.5V SSTL1.5V SSTL1.5V SSTL1.5V SSTL1.5V SSTL1.8V SSTL1.8V SSTL
×4,×8
253
Lag262
C3, I3VCCL = 1.1VTCCS (ps)Lead—
Lag—
C4, I4VCCL = 1.1VTCCS (ps)Lead—
Lag—
C4L, I4LVCCL = 1.1VTCCS (ps)Lead—
Lag—
C4L, I4LVCCL = 0.9VTCCS (ps)Lead—
Lag—
×4, ×8293284341332——————
×4, ×8293284341373——————
×4, ×8169470217496258528258528——
×4, ×8169470217496258528258528——
×4, ×8×4, ×8
229316
246168
230318
355239
250346
388260
250346
388260
350446
488360
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Figure1–7 and Figure1–8 show the model of the circuit that is represented by the output timing of the QuartusII software for differential outputs with single and multiple external resistors.
Figure1–7.Output Delay Timing Reporting Setup Modeled by QuartusII Software for Differential Outputs with Single External Resistor
Non-DedicatedDifferential Outputs VMEASRPVMEASRD
Figure1–8.Output Delay Timing Reporting Setup modeled by QuartusII Software for Differential Outputs with Three External Resistor
Non-DedicatedDifferential Outputs VMEASRSRPRDVMEASRSTable1–39.Output Timing Measurement Methodology for Output Pins(Part 1 of 3)
I/O Standard
RS
3.3-V LVTTL3.3-V LVCMOS3.0-V LVTTL3.0-V LVCMOS2.5-V1.8-V1.5-V1.2-VPCIPCI-X
SSTL-2 CLASSISSTL-2 CLASSIISSTL-18 CLASSISSTL-18 CLASSIISSTL-15 CLASSISSTL-15 CLASSII1.8-V HSTL CLASSI
——————————252525252525—
RD—————————————————
RT——————————50255025502550
Loading and TerminationsRP—————————————————
VCCIO3.1353.1352.852.852.3751.711.4251.142.852.852.3252.3251.661.661.3751.3751.66
VCCPD3.1353.1352.852.852.3752.3752.3752.3752.852.852.3252.3252.3252.3252.3252.3252.325
VCC1.051.051.051.051.051.051.051.051.051.051.021.021.021.021.021.021.02
VTT——————————1.251.250.900.900.750.750.90
CL (pF)0000000010100000000
Measurement
PointVMEAS (v)1.56751.56751.4251.4251.18750.8550.71250.571.4251.4251.16251.16250.830.830.68750.68750.83
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Table1–45 specifies EP3SL50 column pins output timing parameters for single-ended I/O standards.
Table1–45.EP3SL50 Column Pins output Timing Parameters (Part 1 of 7)
ParameterI/O Standard
Current StrengthFast ModelIndustrialCommercial3.0181.5832.9391.5052.9101.4742.8961.4602.9561.5212.8851.4492.8601.4252.8531.4193.0161.5802.9491.5152.9111.4762.8891.453
3.2391.7673.1501.6783.1181.6453.1041.6303.1721.7003.0951.6223.0671.5943.0601.5873.2481.7763.1631.6913.1261.6533.0991.626
C2
VCCL=1.1V
C3
VCCL=1.1V
C4
VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3
VCCL=1.1V
I4
VCCL=1.1V
VCCL=1.1V
I4L
VCCL=0.9V
ClockGCLK
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
tco4.5102.2074.4072.1044.3402.0374.3192.0164.4372.1354.3152.0124.2861.9834.2781.9744.5442.2414.4402.1384.3722.0694.3372.034
4.8965.3905.2572.3122.5292.5344.7845.2735.1402.2012.4122.4174.7145.2035.0702.1302.3422.3474.6915.1755.0422.1062.3142.3194.8135.3025.1692.2302.4422.4474.6875.1715.0382.1032.3102.3154.6605.1465.0132.0762.2842.2894.6515.1375.0042.0672.2752.2804.9325.4295.2962.3492.5882.5934.8215.3135.1802.2382.4942.4994.7495.2395.1062.1652.4302.4354.7105.1975.0642.1272.4072.412
5.4852.4755.3682.3585.2982.2885.2702.2605.3972.3885.2662.2565.2412.2305.2322.2215.5242.5345.4082.4405.3342.3765.2922.353
5.0182.4224.9022.3074.8322.2374.8062.2094.9322.3374.8022.2064.7752.1784.7662.1695.0572.4614.9422.3474.8682.2724.8282.232
5.5102.6405.3902.5205.3232.4525.2902.4185.4222.5525.2852.4145.2602.3885.2512.3785.5522.6815.4342.5635.3582.4865.3142.443
5.3805.5552.6442.4635.2605.4352.5242.3435.1935.3682.4562.2755.1605.3352.4222.2415.2925.4672.5562.3755.1555.3302.4182.2375.1305.3052.3922.2115.1215.2962.3822.2015.4225.5972.6852.5045.3045.4792.5672.3865.2285.4032.4902.3095.1845.3592.4472.266
4mA
GCLK
tco
PLLGCLK
tco
8mA
3.3-V LVTTL
12mA
GCLK
tco
PLLGCLK
tco
GCLK
tco
PLLGCLK
tco
16mA
GCLK
tco
PLLGCLK
tco
4mA
GCLK
tco
PLLGCLK
tco
8mA
3.3-V LVCMOS
12mA
GCLK
tco
PLLGCLK
tco
GCLK
tco
PLLGCLK
tco
16mA
GCLK
tco
PLLGCLK
tco
4mA
GCLK
tco
PLLGCLK
tco
8mA
3.0-V LVTTL
12mA
GCLK
tco
PLLGCLK
tco
GCLK
tco
PLLGCLK
tco
16mA
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP4SGX290NF45I3N中文规格书 - 图文
