Chapter 2: XPHY Architecture
?C: The three-cycle wait from A has been met, so from C onward the input delay (of
NIBBLESLICE[2]) can be changed without glitching. Note that B overlaps with C for one cycle.?After C: The input delay (of NIBBLESLICE[2]) is now reported accurately, and the delay lineupdate is considered complete.The following waveform shows how to update cascaded delays. The waveform updates
NIBBLESLICE[2], but applies to any NIBBLESLICE (note that the bus for each signal, other thanCTRL_CLK, would change too).
Figure 7: Updating a Cascaded Delay Line
?Start: The goal of this waveform is to update a cascaded delay line, which is composed of theinput delay and output delay of a NIBBLESLICE. To update a cascaded delay line, update boththe input and output delays that compose the cascaded delay. Each delay line should beloaded with half of the total desired delay (New delay/2). In this case, the input delay
(RXTX_SEL[2] = 0) is updated first, followed by the output delay (RXTX_SEL[2] = 1). Like thewaveform in Figure 6, this waveform updates the delay through CNTVALUEIN[26:18]. {LD[2],CE[2], INC[2]} = 10x tells the delay line to use CNTVALUEIN to update the delay line, which isthe starting point of this waveform.?A (input delay/output delay): A three-cycle wait is required between updates to the samedelay line (in this case the delay of NIBBLESLICE[2]) to prevent glitching.?B (input delay/output delay): The reported delay might not match the actualdelay being applied. This only affects a delay line that is changed, so the other delay lines inthe nibble are still reported accurately. Note, however, the three cycles shared between A(input delay) and B (output delay) where both the input and output delays of NIBBLESLICE[2]can report a delay that doesn’t match the actual delay being applied.
AM010 (v1.2) April 2, 2024
Versal ACAP SelectIO Resources Architecture Manual
FPGA可编程逻辑器件芯片XC2V1000-6BG575C中文规格书
