FPGA可编程逻辑器件芯片XC2V80-5FF1152I中文规格书 - 图文

Spartan-3 FPGA Family: Functional Description

The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as described in Table16. The clock outputs drive simultaneously; however, the High Frequency mode only supports a subset of the outputs available in the Low Frequency mode. See DLL Frequency Modes, page35. Signals that initialize and report the state of the DLL are discussed in The Status Logic Component, page41.

Table 16:DLL Signals

Mode Support

SignalCLKINCLKFBCLK0CLK90CLK180CLK270CLK2XCLK2X180CLKDV

DirectionInputInputOutputOutputOutputOutputOutputOutputOutput

Accepts original clock signal.

Description

Low Frequency

YesYesYesYesYesYesYesYesYes

High Frequency

YesYesYesNoYesNoNoNoYes

Accepts either CLK0 or CLK2X as feed back signal. (Set CLK_FEEDBACK attribute accordingly).

Generates clock signal with same frequency and phase as CLKIN.

Generates clock signal with same frequency as CLKIN, only phase-shifted 90°.Generates clock signal with same frequency as CLKIN, only phase-shifted 180°.Generates clock signal with same frequency as CLKIN, only phase-shifted 270°.Generates clock signal with same phase as CLKIN, only twice the frequency.Generates clock signal with twice the frequency of CLKIN, phase-shifted 180° with respect to CLKIN.

Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency clock signal that is phase-aligned to CLKIN.

The clock signal supplied to the CLKIN input serves as a reference waveform, with which the DLL seeks to align the

feedback signal at the CLKFB input. When eliminating clock skew, the common approach to using the DLL is as follows: The CLK0 signal is passed through the clock distribution network to all the registers it synchronizes. These registers are either internal or external to the FPGA. After passing through the clock distribution network, the clock signal returns to the DLL via a feedback line called CLKFB. The control block inside the DLL measures the phase error between CLKFB and CLKIN. This phase error is a measure of the clock skew that the clock distribution network introduces. The control block activates the appropriate number of delay elements to cancel out the clock skew. Once the DLL has brought the CLK0 signal in phase with the CLKIN signal, it asserts the LOCKED output, indicating a “lock” on to the CLKIN signal.

DLL Attributes and Related Functions

A number of different functional options can be set for the DLL component through the use of the attributes described in Table17. Each attribute is described in detail in the sections that follow:Table 17:DLL Attributes

Attribute

CLK_FEEDBACK

DLL_FREQUENCY_MODE CLKIN_DIVIDE_BY_2CLKDV_DIVIDE

Description

Chooses between High Frequency and Low Frequency modesHalves the frequency of the CLKIN signal just as it enters the DCM Selects constant used to divide the CLKIN input frequency to generate the CLKDV output frequency

Enables 50% duty cycle correction for the CLK0, CLK90, CLK180, and CLK270 outputs

Values

LOW, HIGH TRUE, FALSE

1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16.TRUE, FALSE

Chooses either the CLK0 or CLK2X output to drive the CLKFB inputNONE, 1X, 2X

DUTY_CYCLE_CORRECTION

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Functional Description

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Functional Description

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Functional Description

The output frequency (fCLKFX) can be expressed as a function of the incoming clock frequency (fCLKIN) as follows:

fCLKFX = fCLKIN(CLKFX_MULTIPLY/CLKFX_DIVIDE)

Equation3

Regarding the two attributes, it is possible to assign any combination of integer values, provided that two conditions are met:??

The two values fall within their corresponding ranges, as specified in Table18.

The fCLKFX frequency calculated from the above expression accords with the DCM’s operating frequencyspecifications.

For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, then the frequency of the output clock signal would be 5/3 that of the input clock signal.

DFS Frequency Modes

The DFS supports two operating modes, High Frequency and Low Frequency, with each specified over a different clock frequency range. The DFS_FREQUENCY_MODE attribute chooses between the two modes. When the attribute is set to LOW, the Low Frequency mode permits the two DFS outputs to operate over a low-to-moderate frequency range. When the attribute is set to HIGH, the High Frequency mode allows both these outputs to operate at the highest possible frequencies.

DFS With or Without the DLL

The DFS component can be used with or without the DLL component:

Without the DLL, the DFS component multiplies or divides the CLKIN signal frequency according to the respective CLKFX_MULTIPLY and CLKFX_DIVIDE values, generating a clock with the new target frequency on the CLKFX and CLKFX180 outputs. Though classified as belonging to the DLL component, the CLKIN input is shared with the DFS component. This case does not employ feedback loop; therefore, it cannot correct for clock distribution delay.

With the DLL, the DFS operates as described in the preceding case, only with the additional benefit of eliminating the clock distribution delay. In this case, a feedback loop from the CLK0 output to the CLKFB input must be present.

The DLL and DFS components work together to achieve this phase correction as follows: Given values for the

CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL selects the delay element for which the output clock edge coincides with the input clock edge whenever mathematically possible. For example, when CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, the input and output clock edges will coincide every three input periods, which is equivalent in time to five output periods.

Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values achieve faster lock times. With no factors common to the two attributes, alignment will occur once with every number of cycles equal to the CLKFX_DIVIDE value. Therefore, it is

recommended that the user reduce these values by factoring wherever possible. For example, given CLKFX_MULTIPLY = 9 and CLKFX_DIVIDE = 6, removing a factor of three yields CLKFX_MULTIPLY = 3 and CLKFX_DIVIDE = 2. While both value-pairs will result in the multiplication of clock frequency by 3/2, the latter value-pair will enable the DLL to lock more quickly.

Table 18:DFS Attributes

Attribute

DFS_FREQUENCY_MODECLKFX_MULTIPLYCLKFX_DIVIDE

Frequency multiplier constantFrequency divisor constant

Description

Chooses between High Frequency and Low Frequency modes

Values

Low, High

Integer from 2 to 32Integer from 1 to 32

Table 19:DFS Signals

SignalCLKFXCLKFX180

DirectionOutputOutput

Description

Multiplies the CLKIN frequency by the attribute-value ratio (CLKFX_MULTIPLY/CLKFX_DIVIDE) to generate a clock signal with a new target frequency.

Generates a clock signal with same frequency as CLKFX, only shifted 180° out-of-phase.

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Functional Description

Configuration

Spartan-3 devices are configured by loading application specific configuration data into the internal configuration memory. Configuration is carried out using a subset of the device pins, some of which are \others, indicated by the term \Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M0, M1, and M2 are Dedicated pins. The mode pin settings are shown in Table26.Table 26:Spartan-3 FPGAs Configuration Mode Pin Settings

Configuration Mode(1)Master Serial Slave SerialMaster Parallel Slave Parallel JTAGNotes:

1.2.

The voltage levels on the M0, M1, and M2 pins select the configuration mode.The daisy chain is possible only in the Serial modes when DOUT is used.

M001101

M101110

M201011

Synchronizing Clock

CCLK OutputCCLK InputCCLK OutputCCLK Input TCKInput

Data Width

11881

Serial DOUT(2)

YesYesNoNoNo

The HSWAP_EN input pin defines whether the I/O pins that are not actively used during configuration have pull-up resistors

during configuration. By default, HSWAP_EN is tied High (via an internal pull-up resistor if left floating) which shuts off the pull-up resistors on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during configuration. The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a pull-up resistor to VCCAUX during configuration, regardless of the value on the HSWAP_EN pin. Similarly, the dual-purpose INIT_B pin has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM, depending on the package style.

Depending on the chosen configuration mode, the FPGA either generates a CCLK output, or CCLK is an input accepting an externally generated clock.

A persist option is available which can be used to force the configuration pins to retain their configuration function even after device configuration is complete. If the persist option is not selected then the configuration pins with the exception of CCLK, PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan related pins. The persist feature is valuable in applications that readback configuration data after entering the User mode.Table27 lists the total number of bits required to configure each FPGA as well as the PROMs suitable for storing those bits. See DS123: Platform Flash In-System Programmable Configuration PROMs data sheet for more information.Table 27:Spartan-3 FPGA Configuration Data

DeviceXC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000

File Sizes439,2641,047,6161,699,1363,223,4885,214,7847,673,02411,316,86413,271,936

Xilinx Platform Flash PROM

Serial Configuration

XCF01SXCF01SXCF02SXCF04SXCF08PXCF08PXCF16PXCF16P

Parallel Configuration

XCF08PXCF08PXCF08PXCF08PXCF08PXCF08PXCF16PXCF16P

The maximum bitstream length that Spartan-3 FPGAs support in serial daisy-chains is 4,294,967,264 bits (4Gbits), roughly equivalent to a daisy-chain with 323 XC3S5000 FPGAs. This is a limit only for serial daisy-chains where configuration data is passed via the FPGA’s DOUT pin. There is no such limit for JTAG chains.

DS099 (v3.1) June 27, 2013Product Specification