Chapter4
User Primitives
The configuration primitives described in this chapter are provided for users to access FPGA configuration resources during or after FPGA configuration. For additional
information and instantiation templates, refer to UG615, Spartan-6 Libraries Guide for HDL Designs.
BSCAN_SPARTAN6
JTAG is a standard four-pin interface: TCK, TMS, TDI, and TDO. Many applications are built around this interface. The JTAG TAP controller is a dedicated state machine inside the configuration logic. BSCAN_SPARTAN6 provides access between the JTAG TAP controller and user logic in fabric. There are up to four instances of BSCAN_SPARTAN6 for each device. Each instance of this design element can handle one JTAG USER instruction
(USER1 through USER4) as set with the JTAG_CHAIN attribute. To handle all four USER instructions, four of these elements can be instantiated, and the JTAG_CHAIN attribute must be set appropriately. Table4-1 lists the BSCAN_SPARTAN6 port descriptions. Table 4-1:BSCAN_SPARTAN6 Port DescriptionsSignal Name SEL
TypeOutput
Function
Active-High interface selection output. SEL=1 when the JTAG instruction register holds the corresponding (USER1, USER2, USER3, or USER4) instruction. Change in Update_IR state. SEL changes on the falling edge of TCK in the UPDATE_IR state of the TAP controller.
Active-High reset output. RESET=1 during the TEST-LOGIC-RESET state, PROGRAM_B, or during
power-up. This signal is deasserted on the falling edge of TCK.Fed through directly from the FPGA TDI pin.
DRCK is the same as TCK in the Capture_DR and Shift_DR states. If the interface is not selected by the instruction register, DRCK remains High.
Active-High pulse indicating the Capture_DR state. This signal is asserted on the falling edge of TCK.
Active-High pulse indicating the Update_DR state. This signal is asserted on the falling edge of TCK.
Active-High pulse indicating the Shift_DR state. This signal is asserted on the falling edge of TCK. Indicates JTAG is in Run Test/Idle state.
RESETOutput
TDIDRCK
OutputOutput
CAPTUREUPDATESHIFTRUNTEST
OutputOutputOutputOutput
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Chapter 5:Configuration Details
Table 5-1:Spartan-6 FPGA Dedicated Configuration Pins (Cont’d)
Type(1)
Description
Pin Name
RFUSECMPCS_B
Notes:
InputReserved
Pulldown for eFUSE programming.(4)Leave unconnected or pull up.
1.The Bidirectional type describes a pin that is bidirectional under all conditions. If the pin is an input for some configuration modes or an
output for others, it is listed as an Input or Output type. For termination settings of configuration pins, see Table5-2.2.Pulsing PROGRAM_B does not reset the JTAG TAP state machine.
3.All JTAG pins and the SUSPEND pin are powered by VCCAUX; DONE and PROGRAM_B are powered by VCCO_2 supplies.4.Only available in 6SLX75, 6SLX75T, 6SLX100, 6SLX100T, 6SLX150, and 6SLX150T devices. For more information on eFUSEprogramming, refer to eFUSE, page93.
FPGA I/O Pin Settings During Configuration
Some of the FPGA pins used during configuration have dedicated pull-up resistors during configuration. However, all user I/O pins have optional pull-up resistors that can be enabled during the configuration process (initializing and programming). During
configuration, a single control line determines whether the pull-up resistors are enabled or disabled. The pin name is HSWAPEN (see Table5-2).
Table 5-2:
Spartan-6 FPGA Configuration Pin Termination
Pre-Configuration
Pin
CCLKD15-D0CSO_BA25-A0(1)SCP7-SCP0DOUT/BUSYHSWAPENPROGRAM_BDONEINIT_BTDITMSTCKTDOM1, M0FCS_BFOE_B
HSWAPEN = 0(enabled)Pull-up to VCCO_2Pull-up to VCCO_2Pull-up to VCCO_2Pull-up to VCCO_1Pull-up to VCCO_0Pull-up to VCCO_1Pull-up to VCCO_0Pull-up to VCCO_2Pull-up to VCCO_2Pull-up to VCCO_2Pull-up to VCCAUXPull-up to VCCAUXPull-up to VCCAUXPull-up to VCCAUXPull-up to VCCO_2Pull-up to VCCO_1Pull-up to VCCO_1
HSWAPEN = 1(disabled)No terminationNo terminationNo terminationNo terminationNo terminationNo terminationPull-up to VCCO_0Pull-up to VCCO_2Pull-up to VCCO_2Pull-up to VCCO_2Pull-up to VCCAUXPull-up to VCCAUXPull-up to VCCAUXPull-up to VCCAUXPull-up to VCCO_2No terminationNo termination
User I/OUser I/OUser I/OUser I/OUser I/OUser I/OUser I/O
BitGen -g ProgPin(2)
BitGen -g DonePin(2) -g DriveDoneUser I/O
BitGen -g TdiPin(2)BitGen -g TmsPin(2)BitGen -g TckPin(2)BitGen -g TdoPin(2)User I/OUser I/OUser I/O
Post-Configuration
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UG380 (v2.11) March 22, 2019
Configuration Pins
Table 5-2:Spartan-6 FPGA Configuration Pin Termination (Cont’d)
Pre-Configuration
Post-Configuration
User I/OUser I/OUser I/O
User I/O if Suspend feature is not used(4)SUSPEND pin(3)(4)User I/OUser I/OUser I/OUser I/O
Pin
FWE_BMOSI/CSI_BRDWR_BAWAKESUSPENDHDCLDCUSERCCLKOther I/O
(not used during configuration)
Notes:
HSWAPEN = 0(enabled)Pull-up to VCCO_1Pull-up to VCCO_2Pull-up to VCCO_2Pull-up to VCCO_1No terminationPull-up to VCCO_1Pull-up to VCCO_1Pull-up to VCCO_2Pull-up to VCCO
HSWAPEN = 1(disabled)No terminationNo terminationNo terminationNo terminationNo terminationNo terminationNo terminationNo terminationNo termination
1.A24/A25 are in bank 5 in the 6SLX75/T devices and larger densities and in FG676 and larger packages. Then the pull-up is toVCCO_5.
2.Setting the BitGen options configures the termination on the respective pin. Not setting an option defaults to Pull-up. Refer to theBitGen section of UG628, Command Line Tools User Guide, for software settings.
3.The SUSPEND pin must be Low during power-up. Connection of an external pull-down resistor ensures this condition.4.For more details on the Suspend feature, refer to UG394, Spartan-6 FPGA Power Management User Guide.
Floating signal levels are problematic in CMOS logic systems. Other logic components in the system can require a valid input level from the FPGA. The internal pull-up resistors generate a logic High level on each pin. Generally, a device driving signals into the FPGA can overcome the pull-up resistor. Similarly, an individual pin can be pulled down using an appropriately sized external pull-down resistor.
In hot-swap or hot-insertion applications, the pull-up resistors provide a potential current path to the I/O power rail. Turning off the pull-up resistors disables this potential path. However, then external pull-up or pull-down resistors can be required on each individual I/O pin.
During power-up or at reconfiguration following PROG_B assertion, the I/O pull-ups may be enabled until the device begins configuration.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Configuration Sequence
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 5:Configuration Details
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
FPGA可编程逻辑器件芯片XC2S150-5CSG144I中文规格书 - 图文
