FPGA可编程逻辑器件芯片EP3C10U256I7N中文规格书

2.Intel Agilex I/O Features and UsageUG-20214 | 2021.04.05

The TCL script creates a qii directory that contains the ed_synth.qpf project file.You can open and compile this project in the Intel Quartus Prime software.

2.3.2.6.2. GPIO Intel FPGA IP Simulation Design Example

The simulation design example uses your GPIO IP parameter settings to build the IPinstance connected to a simulation driver. The driver generates random traffic andinternally checks the legality of the out going data.

Using the design example, you can run a simulation using a single command,

depending on the simulator that you use. The simulation demonstrates how you canuse the GPIO IP.

Generating and Using the Design Example

To generate the simulation design example from the source files for a Verilogsimulator, run the following command in the design example directory:

quartus_sh -t make_sim_design.tcl

To generate the simulation design example from the source files for a VHDL simulator,run the following command in the design example directory:

quartus_sh -t make_sim_design.tcl VHDL

The TCL script creates a sim directory that contains subdirectories—one for eachsupported simulation tool. You can find the scripts for each simulation tool in thecorresponding directories.

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3.Intel Agilex I/O Termination

3.1. Single-Ended I/O Termination in Intel Agilex Devices

Intel Agilex devices support on-chip termination for single-ended I/O standards. OCTmaintains signal quality, saves board space, and reduces external component costs.

Figure 31.

RS and RT OCT

This figure shows the single-ended termination schemes supported in Intel Agilex devices. RT1 and RT2 aredynamic parallel terminations and are enabled only if the device is receiving. In bidirectional applications, RT1and RT2 are automatically switched on when the device is receiving and switched off when the device is driving.Driving DeviceVCCIOReceiving DeviceVCCIO2 × RT2Z0 = 50 ΩVREF2 × RT12 × RT2GND2 × RT1RSGND3.1.1. Single-Ended I/O Standard OCT Termination

Serial (RS) and parallel (RT) OCT provides I/O impedance matching and terminationcapabilities. OCT maintains signal quality, saves board space, and reduces externalcomponent costs.

The OCT calibration circuit uses the impedance of the external resistor that isconnected to the RZQ pin as reference. The impedance of the I/O buffer is

continuously altered until the target impedance is achieved during OCT calibration.The targeted impedance is achieved when the impedance of I/O buffer reaches apredetermined ratio to the reference resistance.

Table 26.

OCT Schemes Supported in Intel Agilex Devices

Direction

Output

OCT SchemesRS OCT with calibrationRS OCT without calibration

InputBidirectional

RT OCT with calibrationDynamic RS and RT OCT

ISO

9001:2015Registered

3.Intel Agilex I/O TerminationUG-20214 | 2021.04.05

3.1.1.1. RS OCT

Intel Agilex devices support RS OCT with and without calibration for single-ended andvoltage-referenced I/O standards.

OCT Scheme

RS without calibration

???

Description

Only supported on output buffer.

Driver-impedance matching provides the I/O driver with a controlled outputimpedance that closely matches the impedance of the transmission line.The OCT calibration circuit uses the impedance of the external resistor that isconnected to the RZQ pin as reference. The impedance of the I/O buffer iscontinuously altered until the target impedance is achieved during OCT

calibration. The targeted impedance is achieved when the impedance of I/Obuffer reaches a predetermined ratio to the reference resistance.

Calibration occurs at the end of device configuration. When the calibrationcircuit finds the correct impedance, the circuit powers down and stopschanging the characteristics of the drivers.

You may trigger re-calibration during user-mode.

RS with calibration

?

?

Figure 32.

RS OCT Without Calibration

This figure shows the RS as the intrinsic impedance of the output transistors.DriverSeries TerminationVCCIOReceivingDeviceRSZ0 = 50 ΩRSGNDFigure 33.

RS OCT with Calibration

This figure shows the RS as the intrinsic impedance of the output transistors.DriverSeries TerminationVCCIOReceivingDeviceRSZ0 = 50 ΩRSGNDSend Feedback