Pin NameMGTHAVCCMGTHAVCCRXMGTHAVTTMGTHAVCCPLL
DirectionInputInputInputInput
Description
Analog supply for the receiver and transmitter internal circuits. In Virtex-6 HXT devices containing GTH transceivers.
Analog supply for the PLL and the receiver equalizers. In Virtex-6 HXT devices containing GTH transceivers.
Analog supply for the transmit driver. In Virtex-6 HXT devices containing GTH transceivers.
Analog supply for the reference clock buffer and the PLL. In Virtex-6 HXT devices containing GTH transceivers.
GND reference for the GTH transceiver internal circuitry. These pins should be connected to the PCB power supply GND reference plane. In Virtex-6 HXT devices containing GTH transceivers.
GTH Quad positive differential reference clock. In Virtex-6 HXT devices containing GTH transceivers.
GTH Quad negative differential reference clock. In Virtex-6 HXT devices containing GTH transceivers.
GTXE1 positive differential reference clock. GTXE1 negative differential reference clock.
Precision reference resistor pin for internal calibration termination. Always located in Bank 115.(4)
Precision reference resistor pin for internal calibration termination. Always located in Bank 115.(4)
Internal precision current, voltage, and resistor references for the GTH Quad. Connect this pin to a 1KΩ resistor with the other terminal of the resistor connected to GND. In Virtex-6 HXT devices containing GTH transceivers.Reserved. No Connection; leave floating. In Virtex-6 HXT devices containing GTH transceivers.
MGTHAGNDInput
MGTREFCLKPMGTREFCLKNMGTREFCLK0/1PMGTREFCLK0/1NMGTAVTTRCALMGTRREF
InputInputInputInputN/AInput
MGTRBIASInput
RSVD
Notes:
N/A
1.All dedicated pins (JTAG and configuration) are powered by VCC_CONFIG (VCC_0).
2.VCCO pins in unbonded banks must be connected to the VCCO for that bank for package migration. Do NOT connect unbondedVCCO pins to different supplies. Without a package migration requirement, VCCO pins in unbonded banks can be left unconnectedor tied to a common supply (VCCO or ground).
3.For more information on connecting the System Monitor pins, see Virtex-6 FPGA System Monitor User Guide.
4.The FF484 and FF784 contain MGTAVCC and MGTAVTT pins. All other packages contain MGTAVCC_N/_S pins. All the respective MGTAV* supply pins are connected via planes in the package to the GTXs. The MGTAVCC and MGTAVTT supply all GTXs in adevice. The MGTAVCC_N and MGTAVTT_N supply all GTXs in the upper half (North) and MGTAVCC_S and MGTAVTT_S supply all GTXs in the lower half (South). If no GTXs are used in the lower half, then the *_S supply pins can be connected to GND. All *_N pins must always be connected to a supply because the calibration resistor resides in the upper half of the part (bank_115). For more information consult the Virtex-6 FPGA RocketIO GTX Transceiver User Guide.
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2018
Die Level Bank Numbering and Clock Pins Overview
Figure1-10 shows the I/O and transceiver banks for the XC6VHX380T. The black dots denote the global clock banks.
X-Ref Target - Figure 1-10GTX/GTHBanks108(2,5)108(2,5)HROWIOCLBanks28(1)28(1)27(1)27(1)26(1)26(1)25252424232322(3)22(3)21(1,3)21(1,3)20(1,3,7)20(1,3,7)CenterBankCLBCLBCLBCLBCLBCLB0CFG0CFG0CFG0CFGCLBCLBCLBCLBCLBCLBCLBCLBMMCM17IOCRBanks38(1)38(1)37(1)37(1)36(1)36(1)3535343433(3)33(3)32(3)32(3)31(1,3)31(1,3)30(1,3,7)30(1,3,7)GTX/GTHBanks118(2)118(2)117(2)117(2)116(2)116(2)115115114114113113112(4)112(4)111(4,6)111(4,6)110(4,6)110(4,6)MGTAVTTRCALMGTRREFQuadGTXQuadGTHCMTMMCM16MMCM15107(2,5)107(2,5)106(2,5)106(2,5)CMTMMCM14MMCM13CMTMMCM12MMCM11MGTAVTTRCALMGTRREF105105104104103103102(4)102(4)101(4)101(4)100(4)100(4)CMTMMCM10MMCM09CMTMMCM08MMCM07CMTMMCM06MMCM05CMTMMCM04MMCM03CMTMMCM02MMCM01CMTMMCM00Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2018
Chapter 2:Pinout Tables
Table 2-1:FF484 Package—LX75T and LX130T (Cont’d)
Bank151515151515151515151515151515151515151515151515151515152424242424
Pin Description
Pin Number
K17L17E19D19K19J19D20E20C22D22E21E22F21F22J20K20H17H18G21H21L18L19H20G20J22H22K21K22T13U13T17U18T16
No Connect (NC)
IO_L6P_SM11P_15IO_L6N_SM11N_15IO_L7P_SM12P_15IO_L7N_SM12N_15IO_L8P_SRCC_15IO_L8N_SRCC_15IO_L9P_MRCC_15IO_L9N_MRCC_15IO_L10P_MRCC_15IO_L10N_MRCC_15IO_L11P_SRCC_15IO_L11N_SRCC_15IO_L12P_SM13P_15IO_L12N_SM13N_15IO_L13P_SM14P_15IO_L13N_SM14N_15IO_L14P_15IO_L14N_VREF_15IO_L15P_SM15P_15IO_L15N_SM15N_15IO_L16P_VRN_15IO_L16N_VRP_15IO_L17P_15IO_L17N_15IO_L18P_15IO_L18N_15IO_L19P_15IO_L19N_15IO_L0P_GC_24IO_L0N_GC_24IO_L1P_GC_24IO_L1N_GC_24IO_L2P_D15_24
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2018
Chapter 4:Mechanical Drawings
RF784 Flip-Chip Fine-Pitch BGA Package Specifications
(1.00mm Pitch)
X-Ref Target - Figure 4-3ug365_c4_13_11111Figure 4-3:RF784 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2018
Chapter 4:Mechanical Drawings
FFV1759 Flip-Chip Fine-Pitch BGA Package Specifications
(1.00mm Pitch)
X-Ref Target - Figure 4-9Figure 4-9:FFV1759 Flip-Chip Fine-Pitch BGA Package Specification
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2018
FPGA可编程逻辑器件芯片XCZU4EG-2FBVB900I中文规格书 - 图文
