Figure1–7 and Figure1–8 show the model of the circuit that is represented by the output timing of the QuartusII software for differential outputs with single and multiple external resistors.
Figure1–7.Output Delay Timing Reporting Setup Modeled by QuartusII Software for Differential Outputs with Single External Resistor
Non-DedicatedDifferential Outputs VMEASRPVMEASRD
Figure1–8.Output Delay Timing Reporting Setup modeled by QuartusII Software for Differential Outputs with Three External Resistor
Non-DedicatedDifferential Outputs VMEASRSRPRDVMEASRSTable1–39.Output Timing Measurement Methodology for Output Pins(Part 1 of 3)
I/O Standard
RS
3.3-V LVTTL3.3-V LVCMOS3.0-V LVTTL3.0-V LVCMOS2.5-V1.8-V1.5-V1.2-VPCIPCI-X
SSTL-2 CLASSISSTL-2 CLASSIISSTL-18 CLASSISSTL-18 CLASSIISSTL-15 CLASSISSTL-15 CLASSII1.8-V HSTL CLASSI
——————————252525252525—
RD—————————————————
RT——————————50255025502550
Loading and TerminationsRP—————————————————
VCCIO3.1353.1352.852.852.3751.711.4251.142.852.852.3252.3251.661.661.3751.3751.66
VCCPD3.1353.1352.852.852.3752.3752.3752.3752.852.852.3252.3252.3252.3252.3252.3252.325
VCC1.051.051.051.051.051.051.051.051.051.051.021.021.021.021.021.021.02
VTT——————————1.251.250.900.900.750.750.90
CL (pF)0000000010100000000
Measurement
PointVMEAS (v)1.56751.56751.4251.4251.18750.8550.71250.571.4251.4251.16251.16250.830.830.68750.68750.83
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Table1–39.Output Timing Measurement Methodology for Output Pins(Part 3 of 3)
I/O Standard
RS
MINI-LVDS_E_1RMINI-LVDS_E_3RRSDS_E_1RRSDS_E_3R
Notes to Table1–39:
(1)Hyper transport is not supported by StratixIII.(2)LVPECL outputs are not supported by StratixIII.
(3)Quartus timing conditions can be changed using the Advanced I/O Timing feature.(4)VCC is nominally 1.1 V less 50 mV (1.05 V).
(5)Terminated I/O standards require an additional 30 mV IR drop on VCC (1.02 V).(6)Terminated I/O standards required an additional 50 mV IR drop on VCCIO and VCCPD.
Loading and Terminations
RD100100100100
RT————
RP120170120170
VCCIO2.3252.3252.3252.325
VCCPD2.3252.3252.3252.325
VCC1.021.021.021.02
VTT————
CL (pF)0000
Measurement
PointVMEAS (v)1.16251.16251.16251.1625
—120—120
I/O Default Capacitive Loading
See Table1–40 for default capacitive loading of different I/O standards.Table1–40.Default Loading of Different I/O Standards for StratixIII (Part 1 of 2)
I/O Standard
3.3-V LVTTL3.3-V LVCMOS3.0-V LVTTL3.0-V LVCMOS2.5-V LVTTL/LVCMOS1.8-V LVTTL/LVCMOS1.5-V LVTTL/LVCMOS3.0-V PCI3.0-V PCI-XSSTL-2 CLASSISSTL-2 CLASSIISSTL-18 CLASSISSTL-18 CLASSII1.5-V HSTL CLASSI1.5-V HSTL CLASSII1.8-V HSTL CLASSI1.8-V HSTL CLASSII1.2-V HSTL
Differential SSTL-2 CLASSIDifferential SSTL-2 CLASSIIDifferential SSTL-18 CLASSI
Capacitive Load
00000001010000000000000
UnitpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpF
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table1–44.EP3SL50 Row Pins Input Timing Parameters (Part 3 of 3)
ParameterI/O Standard
Fast ModelIndustrial-0.8300.9441.040-0.790-0.8440.9581.026-0.776-0.8440.9581.026-0.776-0.8300.9441.040-0.790-0.8300.9441.040-0.790-0.8210.9351.049-0.799-0.8210.9351.049-0.799-0.8901.0030.904-0.655-0.8901.0030.904-0.655
Commercial-0.8710.9981.036-0.774-0.8831.0101.024-0.762-0.8831.0101.024-0.762-0.8710.9981.036-0.774-0.8710.9981.036-0.774-0.8590.9861.048-0.786-0.8590.9861.048-0.786-0.9251.0510.906-0.645-0.9251.0510.906-0.645
C2
VCCL=1.1V
C3
VCCL=1.1V
C4
VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3
VCCL=1.1V
I4
VCCL=1.1V
VCCL=1.1V
I4L
VCCL=0.9V
ClockUnitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
GCLK
SSTL-15 CLASS I
tsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuth
-1.213-1.321-1.434-1.378-1.646-1.331-1.444-1.390-1.6821.3991.707
1.5261.940
1.6622.164
1.5932.050
1.8582.077
1.5461.942
1.6812.166
1.6162.049
1.8932.123
GCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLK
-1.309-1.493-1.666-1.582-1.604-1.488-1.658-1.571-1.649-1.228-1.331-1.452-1.396-1.664-1.342-1.461-1.407-1.6991.4131.692
1.5361.930
1.6802.146
1.6112.032
1.8762.059
1.5571.931
1.6982.149
1.6332.032
1.9102.106
1.8-V HSTL CLASS I
-1.295-1.483-1.648-1.564-1.586-1.477-1.641-1.554-1.632-1.228-1.331-1.452-1.396-1.664-1.342-1.461-1.407-1.6991.4131.692
1.5361.930
1.6802.146
1.6112.032
1.8762.059
1.5571.931
1.6982.149
1.6332.032
1.9102.106
1.8-V HSTL CLASSII
-1.295-1.483-1.648-1.564-1.586-1.477-1.641-1.554-1.632-1.213-1.321-1.434-1.378-1.646-1.331-1.444-1.390-1.6821.3991.707
1.5261.940
1.6622.164
1.5932.050
1.8582.077
1.5461.942
1.6812.166
1.6162.049
1.8932.123
1.5-V HSTL CLASS I
-1.309-1.493-1.666-1.582-1.604-1.488-1.658-1.571-1.649-1.213-1.321-1.434-1.378-1.646-1.331-1.444-1.390-1.6821.3991.707
1.5261.940
1.6622.164
1.5932.050
1.8582.077
1.5461.942
1.6812.166
1.6162.049
1.8932.123
1.5-V HSTL CLASSII
-1.309-1.493-1.666-1.582-1.604-1.488-1.658-1.571-1.649-1.204-1.311-1.418-1.362-1.630-1.322-1.428-1.374-1.6661.3901.716
1.5161.950
1.6462.180
1.5772.066
1.8422.093
1.5371.951
1.6652.182
1.6002.065
1.8772.139
1.2-V HSTL CLASS I
-1.318-1.503-1.682-1.598-1.620-1.497-1.674-1.587-1.665-1.204-1.311-1.418-1.362-1.630-1.322-1.428-1.374-1.6661.3901.716
1.5161.950
1.6462.180
1.5772.066
1.8422.093
1.5371.951
1.6652.182
1.6002.065
1.8772.139
1.2-V HSTL CLASSII
-1.318-1.503-1.682-1.598-1.620-1.497-1.674-1.587-1.665-1.288-1.413-1.637-1.583-1.845-1.427-1.644-1.593-1.8801.4731.557
1.6201.773
1.8671.921
1.7991.805
2.0601.831
1.6441.769
1.8831.926
1.8191.772
2.0951.880
3.0-V PCI
GCLK PLLGCLK
3.0-V PCI-X
-1.160-1.324-1.421-1.336-1.355-1.313-1.416-1.292-1.402-1.288-1.413-1.637-1.583-1.845-1.427-1.644-1.593-1.8801.4731.557
1.6201.773
1.8671.921
1.7991.805
2.0601.831
1.6441.769
1.8831.926
1.8191.772
2.0951.880
GCLK PLL
-1.160-1.324-1.421-1.336-1.355-1.313-1.416-1.292-1.402
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table1–46 specifies EP3SL50 row pins output timing parameters for single-ended I/O standards.
Table1–46.EP3SL50 Row Pins output Timing Parameters (Part 1 of 4)
ParameterI/O Standard
Current StrengthFast ModelIndustrialCommercial3.1971.4823.1041.4153.0141.3363.2071.4923.0181.3403.1511.4423.0261.3412.9871.3043.0651.3632.9691.2913.1771.4683.0671.3833.0211.326
3.4381.6773.3331.6063.2331.5173.4421.6843.2371.5213.3841.6383.2571.5263.2061.4883.3031.5503.1881.4723.4201.6753.3211.5723.2451.528
C2
VCCL=1.1V
C3
VCCL=1.1V
C4
VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3
VCCL=1.1V
I4
VCCL=1.1V
VCCL=1.1V
I4L
VCCL=0.9V
Clock
GCLK
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
tcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotco
4.7812.0614.6511.9514.5321.8454.7892.0654.5381.8564.7332.0284.5801.8914.4981.8314.6271.9264.4631.8034.8652.1364.7102.0124.5991.928
5.1762.1755.0382.0374.9151.9305.1812.1804.9211.9455.1292.1284.9701.9694.8871.9035.0222.0214.8481.8745.2832.2825.1202.1195.0012.015
5.6842.3725.5402.2285.4122.1005.6892.3775.4182.1065.6412.3295.4772.1655.3892.0775.5302.2185.3502.0385.8132.5015.6432.3315.5172.205
5.5492.3885.4052.2445.2772.1165.5542.3935.2832.1225.5062.3455.3422.1815.2542.0935.3952.2345.2152.0545.6782.5175.5082.3475.3822.221
5.7512.3085.6072.1645.4792.0365.7562.3135.4852.0425.7082.2655.5442.1015.4562.0135.5972.1545.4171.9745.8802.4375.7102.2675.5842.141
5.3052.2955.1642.1545.0372.0465.3112.3015.0432.0585.2622.2525.1002.0905.0142.0165.1542.1444.9741.9865.4222.4125.2552.2455.1322.132
5.8182.4955.6692.3465.5372.2145.8232.5005.5442.2215.7762.4535.6122.2895.5192.1965.6652.3425.4792.1565.9552.6325.7812.4585.6512.328
5.6822.5125.5332.3635.4012.2605.6872.5175.4082.2695.6402.4705.4752.3055.3822.2225.5282.3585.3422.1935.8182.6485.6442.4745.5142.354
5.8282.3035.6792.1545.5472.0225.8332.3085.5542.0295.7862.2615.6212.0965.5282.0035.6742.1495.4881.9635.9642.4395.7902.2655.6602.135
4mA
GCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLK
3.3-V LVTTL
8mA
12mA
3.3-V LVCMOS
4mA
8mA
4mA
3.0-V LVTTL
8mA
12mA
3.0-V LVCMOS
4mA
GCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLL
8mA
4mA
2.5 V
8mA
12mA
Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP4SGX230HF35C2N中文规格书 - 图文
