TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005SYNCHRONOUS DRAM TIMING (CONTINUED)
DEAC
ECLKOUTx
1CExABE[7:0] or BBE[1:0]4AEA[22:14] or BEA[20:12]AEA[12:3] or BEA[10:1]
4AEA13 or BEA11
AED[63:0] or BED[15:0]
12AOE/SDRAS/SOE?
ARE/SDCAS/SADS/SRE?
11AWE/SDWE/SWE?
?
15Bank51211These C64x? devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAMmemory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) andBSDCAS, BSDWE, and BSDRAS (for EMIFB)].?ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAMaccesses.
Figure 31. SDRAM DEAC Command for EMIFA and EMIFB?
TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005SYNCHRONOUS DRAM TIMING (CONTINUED)
MRS
ECLKOUTx
1CExABE[7:0] or BBE[1:0]AEA[22:3] or BEA[20:1]AED[63:0] or BED[15:0]
12AOE/SDRAS/SOE?
8ARE/SDCAS/SADS/SRE?
11AWE/SDWE/SWE?
?
14MRS value512811These C64x? devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAMmemory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) andBSDCAS, BSDWE, and BSDRAS (for EMIFB)].?ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAMaccesses.
Figure 33. SDRAM MRS Command for EMIFA and EMIFB?
MEMORY存储芯片TMS320C6711CGDP中文规格书
