FPGA可编程逻辑器件芯片XCZU9EG-2FFVC900I中文规格书 - 图文

Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1

The Virtex-5 family is fully compliant with the IEEE Standard 1149.1 Test Access Port and Boundary-Scan Architecture. The architecture includes all mandatory elements defined in the IEEE 1149.1 Standard. These elements include the Test Access Port (TAP), the TAP controller, the Instruction register, the instruction decoder, the Boundary-Scan register, and the BYPASS register. The Virtex-5 family also supports a 32-bit Identification register and a Configuration register in full compliance with the standard. Outlined in the following sections are the details of the JTAG architecture for Virtex-5 devices.

If Boundary-Scan is used as part of the product verification in the LXT or SXT, the analog supply voltage pin MGTAVCC of all GTP_DUAL tiles must be powered. The analog supply voltage pin MGTAVCC of all unused GTP_DUAL tiles must be connected to the same supply that supplies VCCINT, which is the power supply pin for the internal core logic.

Test Access Port (TAP)

The Virtex-5 TAP contains four mandatory dedicated pins as specified by the protocol given in Table3-1 and illustrated in Figure3-1, a typical JTAG architecture. Three input pins and one output pin control the 1149.1 Boundary-Scan TAP controller. Optional control pins, such as TRST (Test Reset) and enable pins might be found on devices from other manufacturers. It is important to be aware of these optional signals when interfacing Xilinx devices with parts from different vendors because they might need to be driven. The TAP controller is a state machine (16 states) shown in Figure3-2. The four mandatory TAP pins are outlined in Table3-1.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Chapter 3:Boundary-Scan and JTAG Configuration

Capture-DR:

In this controller state, the data is parallel-loaded into the data registers selected by the current instruction on the rising edge of TCK.

Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR:

These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, and Update-IR states in the Instruction path.

10TEST-LOGIC-RESET0RUN-TEST/IDLE1SELECT-DR-SCAN10CAPTURE-DR0SHIFT-DR1EXIT1-DR0PAUSE-DR01EXIT2-DR1UPDATE-DR10100101SELECT-IR-SCAN10CAPTURE-IR0SHIFT-IR1EXIT1-IR0PAUSE-IR1EXIT2-IR1UPDATE-IR00101NOTE: The value shown adjacent to each state transition in this figurerepresents the signal present at TMS at the time of a rising edge at TCK.

UG191_c3_02_050406

Figure 3-2:Boundary-Scan TAP Controller

Virtex-5 devices support the mandatory IEEE 1149.1 commands, as well as several Xilinx vendor-specific commands. The EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,

IDCODE, USERCODE, and HIGHZ instructions are all included. The TAP also supports internal user-defined registers (USER1, USER2, USER3, and USER4) and configuration/readback of the device.

The Virtex-5 Boundary-Scan operations are independent of mode selection. The

Boundary-Scan mode in Virtex-5 devices overrides other mode selections. For this reason, Boundary-Scan instructions using the Boundary-Scan register (SAMPLE/PRELOAD, INTEST, and EXTEST) must not be performed during configuration. All instructions except the user-defined instructions are available before a Virtex-5 device is configured. After configuration, all instructions are available.

JSTART and JSHUTDOWN are instructions specific to the Virtex-5 architecture and

configuration flow. In Virtex-5 devices, the TAP controller is not reset by the PROGRAM_B pin and can only be reset by bringing the controller to the TLR state. The TAP controller is reset on power up.

For details on the standard Boundary-Scan instructions EXTEST, INTEST, and BYPASS, refer to the IEEE Standard.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1

Boundary-Scan Architecture

Virtex-5 device registers include all registers required by the IEEE 1149.1 Standard. In addition to the standard registers, the family contains optional registers for simplified testing and verification (Table3-2).

Table 3-2:Virtex-5 Device JTAG Registers

Register NameBoundary-Scan RegisterInstruction RegisterBYPASS RegisterIdentification RegisterJTAG Configuration RegisterUSERCODE RegisterUser-Defined Registers (USER1, USER2, USER3, andUSER4)

Register Length3 bits per I/O10 or 14 bits

1 bit32 bits32 bits32 bitsDesign-specific

Description

Controls and observes input, output, and output enable

Holds current instruction OPCODE and captures internal device statusBypasses the deviceCaptures the Device ID

Allows access to the configuration bus when using the CFG_IN or CFG_OUT instructions

Captures the user-programmable codeDesign-specific

Boundary-Scan Register

The test primary data register is the Boundary-Scan register. Boundary-Scan operation is independent of individual IOB configurations. Each IOB, bonded or unbonded, starts as bidirectional with 3-state control. Later, it can be configured to be an input, output, or 3-state only. Therefore, three data register bits are provided per IOB (Figure3-3).

When conducting a data register (DR) operation, the DR captures data in a parallel fashion during the CAPTURE-DR state. The data is then shifted out and replaced by new data during the SHIFT-DR state. For each bit of the DR, an update latch is used to hold the input data stable during the next SHIFT-DR state. The data is then latched during the UPDATE-DR state when TCK is Low.

The update latch is opened each time the TAP controller enters the UPDATE-DR state. Care is necessary when exercising an INTEST or EXTEST to ensure that the proper data has been latched before exercising the command. This is typically accomplished by using the SAMPLE/PRELOAD instruction.

Internal pull-up and pull-down resistors should be considered when test vectors are being developed for testing opens and shorts. The HSWAPEN pin determines whether the IOB has a pull-up resistor. Figure3-3 is a representation of Virtex-5 Boundary-Scan architecture.

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020

Chapter 3:Boundary-Scan and JTAG Configuration

TDI?Notes:

IR[9:6]Reserved

IR[5]DONE

IR[4]INIT(1)

IR[3]ISC_ENABLED

IR[2]ISC_DONE

IR[1:0]0 1

?TDO

1.INIT is the status bit of the INIT_COMPLETE signal.

Figure 3-4:

Virtex-5 Device Instruction Capture Values Loaded into IR as Part of an Instruction Scan

Sequence

BYPASS Register

The other standard data register is the single flip-flop BYPASS register. It passes data serially from the TDI pin to the TDO pin during a bypass instruction. This register is initialized to zero when the TAP controller is in the CAPTURE-DR state.

Identification (IDCODE) Register

Virtex devices have a 32-bit identification register called the IDCODE register. The

IDCODE is based on the IEEE 1149.1 standard, and is a fixed, vendor-assigned value that is used to identify electrically the manufacturer and the type of device that is being

addressed. This register allows easy identification of the part being tested or programmed by Boundary-Scan, and it can be shifted out for examination by using the IDCODE instruction.

The last bit of the IDCODE is always 1 (based on JTAG IEEE 1149.1). The last three hex digits appear as 0x093. IDCODEs assigned to Virtex-5 FPGAs are shown in Table1-13, page29.

JTAG Configuration Register

The JTAG Configuration register is a 32-bit register. This register allows access to the configuration bus and readback operations.

USERCODE Register

The USERCODE instruction is supported in the Virtex-5 family. This register allows a user to specify a design-specific identification code. The USERCODE can be programmed into the device and can be read back for verification later. The USERCODE is embedded into the bitstream during bitstream generation (BitGen -g UserID option) and is valid only after configuration. If the device is blank or the USERCODE was not programmed, the USERCODE register contains 0xFFFFFFFF.

USER1, USER2, USER3, and USER4 Registers

The USER1, USER2, USER3, and USER4 registers are only available after configuration. These four registers must be defined by the user within the design. These registers can be accessed after they are defined by the TAP pins.

The BSCAN_VIRTEX5 library macro is required when creating these registers. This symbol is only required for driving internal scan chains (USER1, USER2, USER3, and USER4). A common input pin (TDI) and shared output pins represent the state of the TAP controller (RESET, SHIFT, and UPDATE). Virtex-5 TAP pins are dedicated and do not require the BSCAN_VIRTEX5 macro for normal Boundary-Scan instructions or operations. For HDL, the BSCAN_VIRTEX5 macro must be instantiated in the design.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1

Using Boundary-Scan in Virtex-5 Devices

Characterization data for some of the most commonly requested timing parameters shown in Figure3-5 are listed in DS202, Virtex-5 Data Sheet: DC and Switching Characteristics, in the Configuration Switching Characteristics table.

TMSTDI

TTAPTCKTTCKTAPTCK

TTCKTDOTDO

Data to be capturedData to be driven out

Data ValidData Valid

UG191_c3_05_050406

Figure 3-5:Virtex-5 Device Boundary-Scan Port Timing Waveforms

For further information on the startup sequence, bitstream, and internal configuration registers referenced here, refer to “Configuration Sequence” in Chapter1.

Configuring through Boundary-Scan

One of the most common Boundary-Scan vendor-specific instructions is the configure instruction. If the Virtex-5 device is configured via JTAG on power-up, it is advisable to tie the mode pins to the Boundary-Scan configuration mode settings: 101 (M2 = 1, M1 = 0, M0= 1).

The configuration flow for Virtex-5 device configuration with JTAG is shown in Figure3-6. The sections that follow describe how the Virtex-5 device can be configured as a single device through the Boundary-Scan or as part of a multiple-device scan chain.

A configured device can be reconfigured by toggling the TAP and entering a CFG_IN instruction after pulsing the PROGRAM pin or issuing the shut-down sequence. (Refer to Figure3-6.)

Designers who wish to implement the Virtex-5 JTAG configuration algorithm are encouraged to use the SVF-based flow provided in Xilinx application note XAPP058.

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020