1.35V DDR3L SDRAM SODIMM
MT8KTF12864HZ – 1GBMT8KTF25664HZ – 2GBMT8KTF51264HZ – 4GBFeatures
?DDR3L functionality and operations supported asdefined in the component data sheet
?204-pin, small-outline dual in-line memory module(SODIMM)
?Fast data transfer rates: PC3-14900, PC3-12800, orPC3-10600
?1GB (128 Meg x 64), 2GB (256 Meg x 64), 4GB (512Meg x 64)
?VDD = 1.35V (1.283–1.45V)?VDD = 1.5V (1.425–1.575V)
?Backward compatible with standard 1.5V (±0.075V)DDR3 systems?VDDSPD = 3.0–3.6V
?Nominal and dynamic on-die termination (ODT) fordata, strobe, and mask signals?Single rank
?Fixed burst chop (BC) of 4 and burst length (BL) of 8via the mode register set (MRS)
?On-board I2C serial presence-detect (SPD) EEPROM?Gold edge contacts?Halogen-free?Fly-by topology
?Terminated control, command, and address busTable 1: Key Timing Parameters
Data Rate (MT/s)SpeedIndustryGradeNomenclature-1G9-1G6-1G4-1G1-1G0-80BPC3-14900PC3-12800PC3-10600PC3-8500PC3-8500PC3-6400CL =131866–––––CL =1116001600––––CL =10133313331333–––tRCDtRPtRCFigure 1: 204-Pin SODIMM (MO-268 R/C B2, B4)
Module height: 30mm (1.181in)
Options
?Operating temperature
–Commercial (0°C ≤ TA ≤ +70°C)?Package
–204-pin DIMM (halogen-free)?Frequency/CAS latency
–1.07ns @ CL = 13 (DDR3-1866)–1.25ns @ CL = 11 (DDR3-1600)–1.5ns @ CL = 9 (DDR3-1333)
Marking
NoneZ-1G9-1G6-1G4
CL = 9133313331333–––CL = 810661066106610661066–CL = 71066106610661066––CL = 6800800800800800800CL = 5667667667667667667(ns)13.12513.12513.12513.1251515(ns)13.12513.12513.12513.1251515(ns)47.12548.12549.12550.62552.552.5PDF: 09005aef84577368
ktf8c128_256_512x64hz.pdf - Rev. K 7/15 EN1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2011 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3modules. All pins listed may not be supported on this module. See Pin Assignments forinformation specific to this module.
Table 7: Pin Descriptions
SymbolAxTypeInputDescriptionAddress inputs: Provide the row address for ACTIVE commands, and the column ad-dress and auto precharge bit (A10) for READ/WRITE commands, to select one locationout of the memory array in the respective bank. A10 sampled during a PRECHARGEcommand determines whether the PRECHARGE applies to one bank (A10 LOW, bankselected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-codeduring a LOAD MODE command. See the Pin Assignments table for density-specific ad-dressing information.Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, orPRECHARGE command is being applied. BA define which mode register (MR0, MR1,MR2, or MR3) is loaded during the LOAD MODE command.Clock: Differential clock inputs. All control, command, and address input signals aresampled on the crossing of the positive edge of CK and the negative edge of CK#.Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-try and clocks on the DRAM.Data mask (x8 devices only): DM is an input mask signal for write data. Input datais masked when DM is sampled HIGH, along with that input data, during a write ac-cess. Although DM pins are input-only, DM loading is designed to match that of theDQ and DQS pins.On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT inputwill be ignored if disabled via the LOAD MODE command.Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.Command inputs: RAS#, CAS#, and WE# (along with S#) define the command beingentered.Reset: RESET# is an active LOW asychronous input that is connected to each DRAMand the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-ized as though a normal power-up was executed.Chip select: Enables (registered LOW) and disables (registered HIGH) the commanddecoder.Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-dress range on the I2C bus.Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-cation to and from the temperature sensor/SPD EEPROM on the I2C bus.Check bits: Used for system error detection and correction.Data input/output: Bidirectional data bus.Data strobe: Differential data strobes. Output with read data; edge-aligned withread data; input with write data; center-aligned with write data.BAxInputCKx,CKx#CKExDMxInputInputInputODTxInputPar_InRAS#, CAS#, WE#RESET#InputInputInput(LVCMOS)InputInputInputI/OI/OI/OSx#SAxSCLCBxDQxDQSx,DQSx#PDF: 09005aef84577368
ktf8c128_256_512x64hz.pdf - Rev. K 7/15 EN4Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2011 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
U5SPD EEPROMWPA0A1A2S0#
DQS0# DQS0 DM0DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7DQ DQ DQ DQ DQ DQ DQ DQZQDM CS# DQS DQS#DQS4# DQS4 DM4DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39DM CS# DQS DQS#DQ DQ DQ DQ U3DQ DQ DQ DQZQSCLSDAVSSSA0SA1VSSBA[2:0] A[15/14/13:0]
RAS#CAS# WE# CKE0 ODT0 RESET# BA[2:0]: DDR3 SDRAMA[15/14/13:0]: DDR3 SDRAMRAS#: DDR3 SDRAM CAS#: DDR3 SDRAM WE#: DDR3 SDRAM CKE0: DDR3 SDRAM ODT0: DDR3 SDRAM RESET#: DDR3 SDRAM
U1DQS1# DQS1 DM1VSSDQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15DQS2# DQS2 DM2VSSDQ DQ DQ DQ DQ DQ DQ DQZQDM CS# DQS DQS#DQS5# DQS5 DM5VSSU9DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23DQS3# DQS3 DM3VSSDQ DQ DQ DQ DQ DQ DQ DQZQDM CS# DQS DQS#DQS6# DQS6 DM6VSSDM CS# DQS DQS#DQ DQ DQ DQ U7DQ DQ DQ DQZQCK0CK0#CK1CK1#
DDR3 SDRAM x 8Clock, control, command, and address line terminations:
DM CS# DQS DQS#DQ DQ DQ DQ U4DQ DQ DQ DQZQU2DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55CKE0, A[15/14/13:0], RAS#, CAS#, WE#, S0#, ODT0, BA[2:0]DDR3 SDRAM VTT
DDR3 SDRAM VDD
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31VSSDQ DQ DQ DQ DQ DQ DQ DQZQDM CS# DQS DQS#DQS7# DQS7 DM7VSSCK CK#VDDSPD
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63DM CS# DQS DQS#DQ DQ DQ DQ U6DQ DQ DQ DQZQSPD EEPROMDDR3 SDRAMControl, command,
and address termination DDR3 SDRAM DDR3 SDRAMDDR3 SDRAMVDDVTTVREFCAVREFDQ
U8VSSVSS
Note:
1.The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and outputdriver.
PDF: 09005aef84577368
ktf8c128_256_512x64hz.pdf - Rev. K 7/15 EN8Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2011 Micron Technology, Inc. All rights reserved.
MEMORY存储芯片MT8KTF51264HZ-1G9P1中文规格书 - 图文
