Chapter3
Boundary-Scan and JTAG Configuration
Introduction
Spartan?-6 devices support IEEE Std 1149.1, defining Test Access Port (TAP) and
boundary-scan architecture. These standards ensure the board-level integrity of individual components and the interconnections between them. In addition to connectivity testing, boundary-scan architecture offers flexibility for vendor-specific instructions, such as configure and verify, which add the capability of loading configuration data directly to FPGAs and compliant memories. TAP and boundary-scan architecture is commonly referred to collectively as JTAG.
Boundary-Scan for Spartan-6 Devices Using IEEE Std 1149.1
The Spartan-6 family is fully compliant with the IEEE Std 1149.1 (TAP and boundary-scan architecture). The architecture includes all mandatory elements defined in IEEE Std 1149.1. These elements include the TAP, the TAP controller, the Instruction register, the instruction decoder, the boundary-scan register, and the BYPASS register. The Spartan-6 family also supports a 32-bit Identification register in full compliance with the standard. Outlined in the following sections are the details of the JTAG architecture for Spartan-6 devices. More details about the JTAG architecture for Spartan-6devices can be found in Chapter10, Advanced JTAG Configurations.
Test Access Port (TAP)
The Spartan-6 FPGA TAP contains four mandatory dedicated pins as specified by the protocol in Spartan-6 devices and in typical JTAG architecture (see Figure10-1, page162). Three input pins and one output pin control the IEEE Std 1149.1 boundary-scan TAP controller. Optional control pins, such as Test Reset (TRST), and enable pins might be found on devices from other manufacturers. It is important to be aware of these optional signals when interfacing Xilinx devices with parts from different vendors because they might need to be driven.
The IEEE Std 1149.1 boundary-scan TAP controller is a state machine (16 states), shown in Chapter10, Advanced JTAG Configurations.
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Chapter 3:Boundary-Scan and JTAG Configuration
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Chapter 4:User Primitives
Table 4-1:BSCAN_SPARTAN6 Port Descriptions (Cont’d)Signal Name TCKTMSTDO
TypeOutputOutputInput
Function
The value of the TCK input pin to the FPGA.The value of the TMS input pin to the FPGA.
TDO input driven from the user fabric logic. This signal is internally sampled on the falling edge before being driven out to the FPGA TDO pin.
ICAP_SPARTAN6
The ICAP_SPARTAN6 primitive works similarly to the SelectMAP configuration interface except it is on the fabric side, and ICAP has a separate read/write bus, as opposed to the bidirectional bus in SelectMAP. ICAP also only supports x16 data width. The general SelectMAP timing diagrams and the SelectMAP bitstream ordering information, as
described in SelectMAP Configuration Interface, page30, are also applicable to ICAP. It allows the user to access configuration registers and readback configuration data after configuration is done.
ICAP data width is 16bits for both input and output.Table 4-2:ICAP_SPARTAN6 Port DescriptionsSignalCLKCEWRITEI[15:0]O[15:0]
TypeInputInputInputInputOutput
ICAP interface clock.
Active-Low ICAP interface select. Equivalent to CSI_B in the SelectMAP interface.
Read/Write control input. 0=WRITE, 1=READ. Equivalent to the RDWR_B signal in the SelectMAP interface.
16-bit-wide ICAP write data bus. The bit ordering is identical tothe SelectMAP interface. See SelectMAP Data Ordering, page39.16-bit-wide ICAP read data bus. The bit ordering is identical to theSelectMAP interface. See SelectMAP Data Ordering in SelectMAPData Ordering, page39. The ICAP output should be captured in adevice register.
The packet buffer must be cleared for read data from a command to be presented on the O[15:0] bus. See Configuration Register Read Procedure (SelectMAP) and Configuration Memory Read Procedure (SelectMAP) for the correct procedure.
BUSY
Output
Active-High busy status. Only used in read operations. BUSY remains Low during writes.
Function
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STARTUP_SPARTAN6
STARTUP_SPARTAN6
The STARTUP_SPARTAN6 primitive provides a fabric interface to allow users to control some of global signals after configuration.
Table 4-3:STARTUP_SPARTAN6 Port Description
Signal Name EOSCLKGSR
TypeOutputInputInput
Function
Active-High. Absolute end of startup.User startup clock.
Active-High global set/reset signal. When this input is asserted, all flip-flops are restored to their initial value in the bitstream.
Clear the battery-backed RAM key when it is set. This signal needs to stay Low for 200ns (four clock cycles) to enable KEYCLEAR function.
Active-High global 3-state signal. When this input is asserted, all user I/Os are 3-stated.
Configuration internal oscillator clock output of approximately 50MHz that can be used as a generic clock source instead of a ring oscillator in the FPGA logic. If this port is not connected in the design, the oscillator is disabled.
Configuration logic main clock output. This signal outputs the clock associated with the current configuration mode. If the FPGA is in a Slave
configuration mode, the clock source is CCLK. If the FPGA is in a Master configuration mode, the clock source is the internal oscillator frequency (as defined by the BitGen option -g ConfigRate). Use the BitGen Persist option to maintain this signal after configuration.
KEYCLEARBInput
GTSCFGMCLK
InputOutput
CFGCLKOutput
DNA_PORT
The DNA_PORT provides access to a dedicated shift register, which can be loaded with the Device DNA data bits (unique ID) for a given Spartan?-6 device. In addition to shifting out the DNA data bits, this component allows for the inclusion of supplemental data bits for additional user data or allow for the DNA data to rollover (repeat DNA data after initial data has been shifted out). This component is primarily used in conjunction with other circuitry to build anti-cloning protection for the FPGA bitstream from possible theft.The DNA_PORT component must be instantiated to be used in a design. The instantiation template is found within the ISE? software. Project Navigator HDL templates. The instance declaration must be placed within the code. All inputs and outputs must be connected to the design to ensure proper operation.
To access the Device DNA data, the shift register must first be loaded by setting the
active-High READ signal for one clock cycle. After the shift register is loaded, the data can be synchronously shifted out by enabling the active-High SHIFT input and capturing the data from the DOUT output port. If desired, additional data can be appended to the end of the 57-bit shift register by connecting the appropriate logic to the DIN port. If DNA data
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Chapter 4:User Primitives
Spartan-6 FPGA Configuration User Guide
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FPGA可编程逻辑器件芯片XC95144XL-7TQ144I中文规格书 - 图文
