Feature Descriptions
Table1-15 lists the SFP+ module RX and TX connections to the FPGA.Table 1-15:
FPGA U1 GTX Bank 113 to SFP+ Module Connections
Schematic Net Name
SFP_RX_NSFP_RX_PSFP_TX_PSFP_TX_N
SFP_TX_DISABLE_TRANS
SFP+ Module (P3)Pin121318193
NameRD_NRD_PTD_PTD_NTX_DISABLE
FPGA (U1) Pin
AL5AL6AM4AM3AP33
Table1-16 lists the SFP+ module control and status connections to the FPGA.Table 1-16:
SFP+ Module Control and Status
Board Connection
Test Point J22
High=Fault
Low=Normal Operation
SFP_TX_DISABLE
Jumper J6
Off=SFP DisabledOn=SFP Enabled
SFP_MOD_DETECT
Test Point J21
High=Module Not PresentLow=Module Present
SFP_RS0
Jumper J38
Jumper Pins 1-2=Full RX BandwidthJumper Pins 2-3=Reduced RX Bandwidth
SFP_RS1
Jumper J39
Jumper Pins 1-2=Full TX BandwidthJumper Pins 2-3=Reduced TX Bandwidth
SFP_LOS
Test Point J20
High=Loss of Receiver SignalLow=Normal Operation
SFP Control/Status
SignalSFP_TX_FAULT
10/100/1000 Tri-Speed Ethernet PHY
[Figure1-2, callout 15]
The VC707 board utilizes the Marvell Alaska PHY device (88E1111) U50 for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports SGMII mode only. The PHY
connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P4) with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in SGMII mode with PHY address 0b00111 using the settings shown in Table1-17. These settings can be overwritten by software commands passed over the MDIO interface.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2024
Feature Descriptions
SGMII GTX Transceiver Clock Generation
[Figure1-2, callout 16]
An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter, 125MHz LVDS clock from a 25MHz crystal (X3). This clock is sent to FPGA U1, Bank 113 GTX
transceiver (clock pins AH8 (P) and AH7 (N)) driving the SGMII interface. Series AC coupling capacitors are present to allow the clock input of the FPGA to set the common mode voltage. Figure1-17 shows the Ethernet SGMII clock source.
X-Ref Target - Figure 1-17C30018pF 50VNPOVDDA_SGMIICLKVDD_SGMIICLKU2X325.00 MHz1X11SGMIICLK_XTAL_OUT3ICS844021I-01Clock GeneratorOEVDDAXTAL_OUTVDDQ0587SGMIICLK_Q0_C_PR3201.0MΩ 5?0118pF 50VNPO2GND2C280.1μF 25VX5RSGMIICLK_Q0_P4GND2X23SGMIICLK_XTAL_IN42XTAL_INGNDNQ06SGMIICLK_Q0_C_NSGMIICLK_Q0_NC290.1μF 25VX5RUG885_c1_17_020612GND_SGMIICLKGND_SGMIICLKGND_SGMIICLKFigure 1-17:Ethernet 125 MHz SGMII GTX Clock
References
Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode Ethernet MAC Product Guide for Vivado Design Suite (PG051) [Ref9] and in the LogiCORE IP Tri-Mode Ethernet MAC v4.5 User Guide (UG138) [Ref13].
The product brief for the Marvell 88E1111 Alaska Gigabit Ethernet Transceiver can be found at the Marvell website [Ref21].
The data sheet can be obtained under NDA with Marvell. Contact information is at the Marvell website [Ref21].
For more information about the ICS844021 device, go to the Integrated Device Technology website [Ref22] and search for part number ICS844021.
USB-to-UART Bridge
[Figure1-2, callout 17]
The VC707 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U44) which allows a connection to a host computer with a USB port. The USB cable is supplied in the VC707 Evaluation Kit (Type-A end to host computer, Type mini-B end to VC707 board connector J17). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the VC707 board.
Xilinx UART IP is expected to be implemented in the FPGA logic. The FPGA supports the
USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications application software (for example, TeraTerm) that runs on the host computer. The VCP device
VC707 Evaluation Board
UG885 (v1.8) February 20, 2024
Chapter 1:VC707 Evaluation Board Features
VC707 Evaluation BoardUG885 (v1.8) February 20, 2024
Feature Descriptions
VC707 Evaluation Board
UG885 (v1.8) February 20, 2024
Feature Descriptions
Table 1-27:J35 VITA 57.1 FMC HPC Connections (Cont’d)
I/O
U1 FPGA
Standard
Pin
J35FMC 1 HPC Pin
K1K4
LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18
H33G33C38C39J37J38E37E38F39E39F36F37H28H29G26G27K22J22M21L21G21G22
K5K7K8K10K11K13K14K16K17K19K20K22K23K25K26K28K29K31K32K34K35K37K38
NCNCNC
FMC1_HPC_HA02_PFMC1_HPC_HA02_NFMC1_HPC_HA06_PFMC1_HPC_HA06_NFMC1_HPC_HA10_PFMC1_HPC_HA10_NFMC1_HPC_HA17_CC_PFMC1_HPC_HA17_CC_NFMC1_HPC_HA21_PFMC1_HPC_HA21_NFMC1_HPC_HA23_PFMC1_HPC_HA23_NFMC1_HPC_HB00_CC_PFMC1_HPC_HB00_CC_NFMC1_HPC_HB06_CC_PFMC1_HPC_HB06_CC_NFMC1_HPC_HB10_P FMC1_HPC_HB10_N FMC1_HPC_HB14_P FMC1_HPC_HB14_N FMC1_HPC_HB17_CC_PFMC1_HPC_HB17_CC_NFMC1_VIO_B_M2C
LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18
E33D33G36G37H38G38C35C36D37D38A35A36J25J26K23J23M22L22J21H21M24L24BANK 36 VCCO
J35 FMC 1
Schematic Net Name
HPC Pin
J2J3J6J7J9J10J12J13J15J16J18J19J21J22J24J25J27J28J30J31J33J34J36J37
NCNC
FMC1_HPC_HA03_PFMC1_HPC_HA03_NFMC1_HPC_HA07_PFMC1_HPC_HA07_NFMC1_HPC_HA11_PFMC1_HPC_HA11_NFMC1_HPC_HA14_PFMC1_HPC_HA14_NFMC1_HPC_HA18_PFMC1_HPC_HA18_NFMC1_HPC_HA22_PFMC1_HPC_HA22_NFMC1_HPC_HB01_PFMC1_HPC_HB01_NFMC1_HPC_HB07_PFMC1_HPC_HB07_NFMC1_HPC_HB11_PFMC1_HPC_HB11_NFMC1_HPC_HB15_PFMC1_HPC_HB15_NFMC1_HPC_HB18_PFMC1_HPC_HB18_N
Schematic Net Name
I/O Standard
U1 FPGA Pin
J39FMC1_VIO_B_M2C
BANK 36 VCCO
K40
Notes:
1.No I/O standards are associated with MGT connections.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2024
FPGA可编程逻辑器件芯片XC2S15-6CS144I中文规格书 - 图文
