大连理工大学数字电路课程设计报告_多功能数字时钟设计说明

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qsg[4] qsg[3] qsg[2] qsg[1] qsg[0] qms[6] qms[5] qms[4] qms[3] qms[2] qms[1] qms[0] qmg[6] qmg[5] qmg[4] qmg[3] qmg[2] qmg[1] qmg[0] qgs[6] qgs[5] qgs[4] qgs[3] qgs[2] qgs[1] qgs[0] qgg[6] qgg[5] qgg[4] qgg[3] qgg[2] qgg[1] qgg[0] qfs[6] qfs[5] qfs[4] qfs[3] qfs[2] qfs[1] qfs[0] qfg[6] qfg[5] qfg[4] OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT PIN_M3 PIN_M2 PIN_P3 PIN_P4 PIN_R2 PIN_W24 PIN_U22 PIN_Y25 PIN_Y26 PIN_AA26 PIN_AA25 PIN_Y23 PIN_Y24 PIN_AB25 PIN_AB26 PIN_AC26 PIN_AC25 PIN_V22 PIN_AB23 PIN_AB24 模式显示高位（默认全灭） PIN_AA23 PIN_AA24 PIN_Y22 PIN_W21 PIN_V21 PIN_V20 PIN_V13 PIN_V14 PIN_AE11 PIN_AD11 PIN_AC12 PIN_AB12 PIN_AF10 PIN_R3 PIN_R4 PIN_R5 PIN_T9 PIN_P7 PIN_P6 PIN_T2 PIN_T3 PIN_R6 PIN_R7 分针低位数码管显示分针高位数码管显示模式显示低位秒针低位数码管显示秒针高位数码管显示 . . .

qfg[3] qfg[2] qfg[1] qfg[0] 4 系统的VHDL设计

OUT OUT OUT OUT PIN_T4 PIN_U2 PIN_U1 PIN_U9

4.1顶层设计 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity liyabin is --实体声明，及系统输入与输出

port(clk,rst,add,dec,selectmode,startmb,startnz,startdjs:in std_logic; qgs,qgg,qss,qsg,qfs,qfg,qms,qmg:buffer std_logic_vector(6 downto 0); ledbs,lednz,leddjs:out std_logic ); end;

architecture data of liyabin is

component mode --模式循环模块元件例化 port(selectmode:in std_logic;

mode:buffer std_logic_vector(2 downto 0) );

end component;

component gnxz --功能选择模块元件例化 port(zt:in std_logic_vector(2 downto 0);

sz1,sz2,sz3,sz4,sz5,sz6:in std_logic_vector(3 downto 0);--时钟显示信号 mb1,mb2,mb3,mb4,mb5,mb6:in std_logic_vector(3 downto 0);--秒表显示信号 nz3,nz4,nz5,nz6:in std_logic_vector(3 downto 0);--闹钟显示信号

djs1,djs2,djs3,djs4,djs5,djs6:in std_logic_vector(3 downto 0);--倒计时显示信号

s1,s2,s3,s4,s5,s6,s7,s8:out std_logic_vector(3 downto 0)--输出，送入显示模块用数码管进行显示 );

end component;

component fp --分频模块元件例化 port(clk,rst:in std_logic;

clk10ms,clk100ms,clk1s:out std_logic); end component;

component sz --时钟模块元件例化

. . .

port(zt:in std_logic_vector(2 downto 0); clk,clk100ms,rst,add,dec:in std_logic;

sz1,sz2,sz3,sz4,sz5,sz6:buffer std_logic_vector(3 downto 0); ledbs: out std_logic );

end component;

component nz --闹钟模块元件例化

port(startnz,add,dec,rst,clk,clk100ms:in std_logic; zt:in std_logic_vector(2 downto 0);

sz2,sz3,sz4,sz5,sz6:in std_logic_vector(3 downto 0);--时钟显示信号 nz3,nz4,nz5,nz6:buffer std_logic_vector(3 downto 0);--闹钟显示信号] lednz:out std_logic --闹钟提示灯输出 );

end component;

component mb --秒表模块元件例化 port(zt:in std_logic_vector(2 downto 0); clk,rst,startmb:in std_logic;

mb1,mb2,mb3,mb4,mb5,mb6:buffer std_logic_vector(3 downto 0) );

end component;

component djs --倒计时模块元件例化

port(rst,startdjs,add,dec,clk,clk100ms:in std_logic; zt:in std_logic_vector(2 downto 0);

djs1,djs2,djs3,djs4,djs5,djs6:buffer std_logic_vector(3 downto 0); leddjs:out std_logic );

end component;

component xs --显示模块元件例化 port(xsin:in std_logic_vector(3 downto 0);-- xsout:out std_logic_vector(6 downto 0) );

end component;

signal clk10ms,clk100ms,clk1s,clk1m,clk1h :std_logic; --分频脉冲信号级进位脉冲信号

signal sz1,sz2,sz3,sz4,sz5,sz6,sz33,sz55:std_logic_vector(3 downto 0);--时钟显示信号

signal nz3,nz4,nz5,nz6:std_logic_vector(3 downto 0);--闹钟显示信号

signal mb1,mb2,mb3,mb4,mb5,mb6:std_logic_vector(3 downto 0);--秒表显示信号 signal djs1,djs2,djs3,djs4,djs5,djs6:std_logic_vector(3 downto 0);--倒计时显

. . .

示信号

signal s1,s2,s3,s4,s5,s6,s7,s8:std_logic_vector(3 downto 0);--显示信号 signal zt:std_logic_vector(2 downto 0);

begin --结构体

------------------------ ------模式循环模块------ ------------------------

u1:mode port map(selectmode,zt); ------------------------ ------功能选择模块----- ------------------------

u2:gnxz port map(zt,sz1,sz2,sz3,sz4,sz5,sz6, mb1,mb2,mb3,mb4,mb5,mb6, nz3,nz4,nz5,nz6, djs1,djs2,djs3,djs4,

s1,s2,s3,s4,s5,s6,s7,s8); ------------------------ --------分频模块-------- ------------------------

u3:fp port map(clk,rst,clk10ms,clk100ms,clk1s); ------------------------ --------时钟模块-------- ------------------------ u4:sz port map(zt,clk1s,clk100ms,rst,add,dec,sz1,sz2,sz3,sz4,sz5,sz6,ledbs); ------------------------ --------闹钟模块------- ------------------------

u5:nz port map(startnz,add,dec,rst,clk1s,clk100ms, zt,sz2,sz3,sz4,sz5,sz6,nz3,nz4,nz5,nz6,lednz); ------------------------ --------秒表模块-------- ------------------------

u6:mb port map(zt,clk10ms,rst,startmb,mb1,mb2,mb3,mb4,mb5,mb6); ------------------------ --------倒计时模块------ ------------------------

u7:djs port map(rst,startdjs,add,dec,clk10ms,clk100ms, zt,djs1,djs2,djs3,djs4,djs5,djs6,leddjs); ----------------------------- ---------显示模块------------ ----------------------------- show1: xs port map(s1,qmg);

. . .

show2: xs port map(s2,qms); show3: xs port map(s3,qfg); show4: xs port map(s4,qfs); show5: xs port map(s5,qsg); show6: xs port map(s6,qss); show7: xs port map(s7,qgg); show8: xs port map(s8,qgs);

end; --结束

4.2 分频模块 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity fp is

port(clk,rst:in std_logic;

clk10ms,clk100ms,clk1s:out std_logic); end;

architecture data of fp is begin

--50兆分频，产生clk1s，作为始时钟的秒计时脉冲 process(clk,rst)

variable num:integer range 0 to 49999999; begin

if rst='0' then num:=0;

elsif rising_edge(clk) then if num=49999999 then num:=0; clk1s<='1'; else

num:=num+1; clk1s<='0'; end if; end if; end process;