Simultaneously Switching Output Guidelines
This section provides guidelines for the maximum allowable number of Simultaneous Switching Outputs (SSOs). These guidelines describe the maximum number of user I/O pins, of a given output signal standard, that should simultaneously switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce.
Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the VCCO rail; High-to-Low transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return. The inductance is associated with
bonding wires, the package lead frame, and any other signal routing inside the package. Other variables contribute to SSO noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage consequently affects internal switching noise margins and ultimately signal quality.
Table49 and Table50 provide the essential SSO guidelines. For each device/package combination, Table49 provides the number of equivalent VCCO/GND pairs. The equivalent number of pairs is based on characterization and will possibly not match the physical number of pairs. For each output signal standard and drive strength, Table50 recommends the maximum number of SSOs, switching in the same direction, allowed per VCCO/GND pair within an I/O bank. The Table50 guidelines are categorized by package style. Multiply the appropriate numbers from Table49 and Table50 to calculate the maximum number of SSOs allowed within an I/O bank. Exceeding these SSO guidelines may result in increased power or ground bounce, degraded signal integrity, or increased system jitter.
SSOMAX/IO Bank = Table49 x Table50
The recommended maximum SSO values assume that the FPGA is soldered on the printed circuit board and that the board uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance introduced by the socket.
The number of SSOs allowed for quad-flat packages (VQ, TQ, PQ) is lower than for ball grid array packages (FG) due to the larger lead inductance of the quad-flat packages. Ball grid array packages are recommended for applications with a large number of simultaneously switching outputs.Table 49:Equivalent VCCO/GND Pairs per Bank
DeviceXC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000Notes:
1.2.3.
The VCCO lines for the pair of banks on each side of the CP132 and TQ144 packages are internally tied together. Each pair of interconnected banks shares three VCCO/GND pairs. Consequently, the per bank number is 1.5.The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. The information in this table also applies to Pb-free packages.
VQ10011––––––
CP132(1)(2)
1.5–––––––
TQ144(1)
1.51.51.5–––––
PQ208222–––––
FT256–333––––
FG320––333–––
FG456––5555––
FG676–––56666
FG900–––––91010
FG1156(2)
––––––1212
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 56:Block RAM Timing
Speed Grade
Symbol
Clock-to-Output TimesTBCKO
When reading from the Block RAM, the time from the active transition at the CLK input to data appearing at the DOUT output
–
2.09
–
2.40
ns
Description
Min
-5
Max
Min
-4
Max
Units
Setup TimesTBDCK
Time from the setup of data at the DIN inputs to the active transition at the CLK input of the Block RAM
0.43
–
0.49
–
ns
Hold TimesTBCKD
Time from the active transition at the Block RAM’s CLK input to the point where data is last held at the DIN inputs
0
–
0
–
ns
Clock TimingTBPWHTBPWLNotes:
1.2.
The numbers in this table are based on the operating conditions set forth in Table32.For minimums, use the values reported by the Xilinx timing analyzer.
Block RAM CLK signal High pulse width
Block RAM CLK signal Low pulse width
1.191.19
∞∞
1.371.37
∞∞
nsns
Clock Distribution Switching Characteristics
Table 57:Clock Distribution Switching Characteristics
Maximum
Description
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I-input to O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0- and I1-inputs. Same as BUFGCE enable CE-inputNotes:
1.
For minimums, use the values reported by the Xilinx timing analyzer.
SymbolTGIOTGSI
Speed Grade-50.360.53
Unitsnsns
-40.410.60
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table58 and Table59) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Table60 through Table63) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Table58 and Table59.
Period jitter and cycle-cycle jitter are two (of many) different ways of characterizing clock jitter. Both specifications describe statistical variation from a mean value.
Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods sampled (usually from 100,000 to more than a million samples for specification purposes). In a histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero.
Delay-Locked Loop (DLL)
Table 58:Recommended Operating Conditions for the DLL
Speed Grade
Symbol
Input Frequency RangesFCLKIN
CLKIN_FREQ_DLL_LFCLKIN_FREQ_DLL_HF
Input Pulse RequirementsCLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN period
FCLKIN ≤ 100 MHzFCLKIN > 100 MHz
LowHighAllAll
40E%––––
Allowable variation of off-chip feedback delay from the DCM output to the CLKFB input
–
60U%
40E%–––––
60U%
--pspsnsns
Frequency for the CLKIN input
LowHigh
18(2)48
167(3)280(3)
18(2)48
167(3)280(3)(4)
MHzMHz
Description
Frequency Mode/FCLKIN Range
Min
-5Max
Min
-4Max
Units
Input Clock Jitter Tolerance and Delay Path Variation(5)CLKIN_CYC_JITT_DLL_LFCLKIN_CYC_JITT_DLL_HFCLKIN_PER_JITT_DLL_LF CLKIN_PER_JITT_DLL_HF CLKFB_DELAY_VAR_EXT
Cycle-to-cycle jitter at the CLKIN input
Period jitter at the CLKIN input
±300±150±1±1
±300±150±1±1
Notes:
1.DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2.3.4.5.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table60.
The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to FBUFG. When set to TRUE,CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM.
Industrial temperature range devices have additional requirements for continuous clocking, as specified in Table64.CLKIN input jitter beyond these limits may cause the DCM to lose lock. See UG331 for more details.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2S300E-FG456中文规格书 - 图文
