Figure1–5.Output Register Clock to Output Timing Diagram
DatainClockClock pad to output Register delayOutput Register micro tCOOutput Register to output pin delayOutputSimulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the QuartusII software and the timing model in the device handbook.
1.Simulate the output driver of choice into the generalized test setup, using values
from Table1–39.2.Record the time to VMEAS at the far end of the PCB trace.
3.Simulate the output driver of choice into the actual PCB trace and load, using the
appropriate IBIS model or capacitance value to represent the load.4.Record the time to VMEAS at the far end of the PCB trace.
5.Compare the results of steps 2 and 4. The increase or decrease in delay should be
added to or subtracted from the I/O Standard Output Adder delays to yield theactual worst-case propagation delay (clock-to-output) of the PCB trace.The QuartusII software reports the timing with the conditions shown in Table1–39 using the above equation. Figure1–6 shows the model of the circuit that is represented by the output timing of the QuartusII software.
Figure1–6.Output Delay Timing Reporting Setup Modeled by QuartusII Software for Single-Ended Outputs and Dedicated Differential Outputs (Note1)
VCCIOVTTOutputpRDRTOutputBufferOutputRSCLGNDVMEASOutputnGNDNote to Figure1–6:
(1)Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay
need to be accounted for with IBIS model simulations.
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Table1–39.Output Timing Measurement Methodology for Output Pins(Part 3 of 3)
I/O Standard
RS
MINI-LVDS_E_1RMINI-LVDS_E_3RRSDS_E_1RRSDS_E_3R
Notes to Table1–39:
(1)Hyper transport is not supported by StratixIII.(2)LVPECL outputs are not supported by StratixIII.
(3)Quartus timing conditions can be changed using the Advanced I/O Timing feature.(4)VCC is nominally 1.1 V less 50 mV (1.05 V).
(5)Terminated I/O standards require an additional 30 mV IR drop on VCC (1.02 V).(6)Terminated I/O standards required an additional 50 mV IR drop on VCCIO and VCCPD.
Loading and Terminations
RD100100100100
RT————
RP120170120170
VCCIO2.3252.3252.3252.325
VCCPD2.3252.3252.3252.325
VCC1.021.021.021.02
VTT————
CL (pF)0000
Measurement
PointVMEAS (v)1.16251.16251.16251.1625
—120—120
I/O Default Capacitive Loading
See Table1–40 for default capacitive loading of different I/O standards.Table1–40.Default Loading of Different I/O Standards for StratixIII (Part 1 of 2)
I/O Standard
3.3-V LVTTL3.3-V LVCMOS3.0-V LVTTL3.0-V LVCMOS2.5-V LVTTL/LVCMOS1.8-V LVTTL/LVCMOS1.5-V LVTTL/LVCMOS3.0-V PCI3.0-V PCI-XSSTL-2 CLASSISSTL-2 CLASSIISSTL-18 CLASSISSTL-18 CLASSII1.5-V HSTL CLASSI1.5-V HSTL CLASSII1.8-V HSTL CLASSI1.8-V HSTL CLASSII1.2-V HSTL
Differential SSTL-2 CLASSIDifferential SSTL-2 CLASSIIDifferential SSTL-18 CLASSI
Capacitive Load
00000001010000000000000
UnitpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpF
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table1–40.Default Loading of Different I/O Standards for StratixIII (Part 2 of 2)
I/O Standard
Differential SSTL-18 CLASSII1.8-V Differential HSTL CLASSI1.8-V Differential HSTL CLASSII1.5-V Differential HSTL CLASSI1.5-V Differential HSTL CLASSII1.2-V Differential HSTL CLASSI1.2-V Differential HSTL CLASSIILVDS
Capacitive Load
00000000
UnitpFpFpFpFpFpFpFpF
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table1–43.EP3SL50 Column Pins Input Timing Parameters (Part 3 of 3)
ParameterI/O Standard
Fast Model
Industrial
Commercial
C2
VCCL=1.1V
C3
VCCL=1.1V
C4
VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3
VCCL=1.1V
I4
VCCL=1.1V
VCCL=1.1V
I4L
VCCL=0.9V
ClockUnitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
1.2-V HSTL CLASS I
GCLKGCLK PLLGCLKGCLK PLLGCLK
tsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuth
-0.8210.9360.821-0.576-0.8130.9280.829-0.584-0.8130.9280.829-0.584-0.9181.0310.724-0.481
-0.8520.9810.909-0.647-0.8400.9690.921-0.659-0.8400.9690.921-0.659-0.9431.0700.816-0.556
-1.229-1.348-1.475-1.413-1.697-1.355-1.481-1.423-1.7331.4101.458
1.5501.656
1.6991.728
1.6261.635
1.9081.650
1.5661.553
1.7131.733
1.6451.638
1.9431.697
-1.070-1.218-1.245-1.180-1.189-1.111-1.241-1.175-1.236-1.219-1.337-1.459-1.397-1.681-1.344-1.466-1.408-1.7181.4001.468
1.5391.667
1.6831.744
1.6101.651
1.8921.666
1.5551.564
1.6981.748
1.6301.653
1.9281.712
1.2-V HSTL CLASSII
-1.080-1.229-1.261-1.196-1.205-1.122-1.256-1.190-1.251-1.219-1.337-1.459-1.397-1.681-1.344-1.466-1.408-1.7181.4001.468
1.5391.667
1.6831.744
1.6101.651
1.8921.666
1.5551.564
1.6981.748
1.6301.653
1.9281.712
3.0-V PCI
GCLK PLLGCLK
3.0-V PCI-X
-1.080-1.229-1.261-1.196-1.205-1.122-1.256-1.190-1.251-1.332-1.466-1.704-1.644-1.925-1.477-1.707-1.651-1.9591.5141.358
1.6711.541
1.9311.499
1.8581.404
2.1411.422
1.6911.431
1.9431.507
1.8741.410
2.1741.471
GCLK PLL
-0.968-1.100-1.013-0.948-0.956-0.986-1.011-0.946-1.005
Table1–44 specifies EP3SL50 row pins input timing parameters for single-ended I/O standards.
Table1–44.EP3SL50 Row Pins Input Timing Parameters (Part 1 of 3)
ParameterI/O Standard
Fast ModelIndustrial-0.8840.9970.910-0.661-0.8840.9970.910-0.661-0.8901.0030.904-0.655
Commercial-0.9141.0400.917-0.656-0.9141.0400.917-0.656-0.9251.0510.906-0.645
C2
VCCL=1.1V
C3
VCCL=1.1V
C4
VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3
VCCL=1.1V
I4
VCCL=1.1V
VCCL=1.1V
I4L
VCCL=0.9V
ClockUnitsnsnsnsnsnsnsnsnsnsnsnsns
GCLK
3.3-V LVTTL
tsuthtsuthtsuthtsuthtsuthtsuth
-1.291-1.412-1.634-1.580-1.842-1.428-1.639-1.588-1.8751.4761.554
1.6191.774
1.8641.924
1.7961.808
2.0571.834
1.6451.768
1.8781.931
1.8141.777
2.0901.885
GCLK PLLGCLK
-1.157-1.325-1.424-1.339-1.358-1.312-1.421-1.297-1.407-1.291-1.412-1.634-1.580-1.842-1.428-1.639-1.588-1.8751.4761.554
1.6191.774
1.8641.924
1.7961.808
2.0571.834
1.6451.768
1.8781.931
1.8141.777
2.0901.885
3.3-V LVCMOS
GCLK PLLGCLK
-1.157-1.325-1.424-1.339-1.358-1.312-1.421-1.297-1.407-1.288-1.413-1.637-1.583-1.845-1.427-1.644-1.593-1.8801.4731.557
1.6201.773
1.8671.921
1.7991.805
2.0601.831
1.6441.769
1.8831.926
1.8191.772
2.0951.880
3.0-V LVTTL
GCLK PLL
-1.160-1.324-1.421-1.336-1.355-1.313-1.416-1.292-1.402
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Table1–44.EP3SL50 Row Pins Input Timing Parameters (Part 2 of 3)
ParameterI/O Standard
Fast ModelIndustrial-0.8901.0030.904-0.655-0.8780.9910.916-0.667-0.9401.0540.930-0.680-0.9301.0440.940-0.690-0.8700.9841.000-0.750-0.8210.9350.973-0.723-0.8210.9350.973-0.723-0.8440.9581.026-0.776-0.8440.9581.026-0.776
Commercial-0.9251.0510.906-0.645-0.9181.0440.913-0.652-0.9821.1090.925-0.663-0.9711.0980.936-0.674-0.9181.0450.989-0.727-0.8600.9870.971-0.709-0.8600.9870.971-0.709-0.8831.0101.024-0.762-0.8831.0101.024-0.762
C2
VCCL=1.1V
C3
VCCL=1.1V
C4
VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3
VCCL=1.1V
I4
VCCL=1.1V
VCCL=1.1V
I4L
VCCL=0.9V
ClockUnitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
GCLK
3.0-V LVCMOS
tsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuth
-1.288-1.413-1.637-1.583-1.845-1.427-1.644-1.593-1.8801.4731.557
1.6201.773
1.8671.921
1.7991.805
2.0601.831
1.6441.769
1.8831.926
1.8191.772
2.0951.880
GCLK PLLGCLK
-1.160-1.324-1.421-1.336-1.355-1.313-1.416-1.292-1.402-1.297-1.426-1.652-1.598-1.860-1.436-1.654-1.603-1.8901.4821.548
1.6331.760
1.8821.906
1.8141.790
2.0751.816
1.6531.760
1.8931.916
1.8291.762
2.1051.870
2.5 V
GCLK PLLGCLK
1.8 V
-1.151-1.311-1.406-1.321-1.340-1.304-1.406-1.282-1.392-1.369-1.491-1.684-1.629-1.895-1.501-1.688-1.635-1.9261.5541.551
1.6981.770
1.9141.914
1.8451.799
2.1111.828
1.7181.772
1.9281.922
1.8621.804
2.1411.879
GCLK PLLGCLK
1.5 V
-1.154-1.321-1.414-1.330-1.351-1.316-1.411-1.325-1.401-1.345-1.459-1.616-1.561-1.827-1.470-1.623-1.570-1.8611.5301.575
1.6661.802
1.8461.982
1.7771.867
2.0431.896
1.6871.803
1.8631.987
1.7971.869
2.0761.944
GCLK PLLGCLK
1.2 V
-1.178-1.353-1.482-1.398-1.419-1.347-1.476-1.390-1.466-1.266-1.358-1.457-1.402-1.668-1.374-1.468-1.415-1.7061.4511.654
1.5651.903
1.6872.141
1.6182.026
1.8842.055
1.5911.899
1.7082.142
1.6422.024
1.9212.099
GCLK PLLGCLK
SSTL-2 CLASS I
-1.257-1.454-1.641-1.557-1.578-1.443-1.631-1.545-1.621-1.211-1.317-1.432-1.378-1.640-1.324-1.437-1.386-1.6731.3961.634
1.5241.869
1.6622.126
1.5942.010
1.8552.036
1.5411.872
1.6762.133
1.6121.979
1.8882.087
GCLK PLLGCLK
-1.237-1.420-1.626-1.541-1.560-1.416-1.623-1.499-1.609-1.211-1.317-1.432-1.378-1.640-1.324-1.437-1.386-1.6731.3961.634
1.5241.869
1.6622.126
1.5942.010
1.8552.036
1.5411.872
1.6762.133
1.6121.979
1.8882.087
SSTL-2 CLASSII
GCLK PLLGCLK
-1.237-1.420-1.626-1.541-1.560-1.416-1.623-1.499-1.609-1.228-1.331-1.452-1.396-1.664-1.342-1.461-1.407-1.6991.4131.692
1.5361.930
1.6802.146
1.6112.032
1.8762.059
1.5571.931
1.6982.149
1.6332.032
1.9102.106
SSTL-18 CLASS I
GCLK PLLGCLK
-1.295-1.483-1.648-1.564-1.586-1.477-1.641-1.554-1.632-1.228-1.331-1.452-1.396-1.664-1.342-1.461-1.407-1.6991.4131.692
1.5361.930
1.6802.146
1.6112.032
1.8762.059
1.5571.931
1.6982.149
1.6332.032
1.9102.106
SSTL-18 CLASSII
GCLK PLL
-1.295-1.483-1.648-1.564-1.586-1.477-1.641-1.554-1.632
Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S20F484I5N中文规格书 - 图文
