SII51002-4.3
Functional Description
Stratix?II devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provides signal interconnects between logic array blocks (LABs), memory block structures (M512 RAM, M4K RAM, and M-RAM blocks), and digital signal processing (DSP) blocks.
Each LAB consists of eight adaptive logic modules (ALMs). An ALM is the StratixII device family’s basic building block of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device.
M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 500 MHz. M512 blocks are grouped into columns across the device in between certain LABs.M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 550 MHz. These blocks are grouped into columns across the device in between certain LABs.
M-RAM blocks are true dual-port memory blocks with 512K bits plusparity (589,824 bits). These blocks provide dedicated true dual-port,simple dual-port, or single-port memory up to 144-bits wide at up to420MHz. Several M-RAM blocks are located individually in the device'slogic array.
DSP blocks can implement up to either eight full-precision 9 × 9-bit multipliers, four full-precision 18 × 18-bit multipliers, or one
full-precision 36 × 36-bit multiplier with add or subtract features. The DSP blocks support Q1.15 format rounding and saturation in the multiplier and accumulator stages. These blocks also contain shift registers for digital signal processing applications, including finite impulse response (FIR) and infinite impulse response (IIR) filters. DSP blocks are grouped into columns across the device and operate at up to 450MHz.
Functional Description
Each StratixII device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enable signals. When used with dedicated clocks, these registers provide exceptional performance and interface support with external memory devices such as DDR and DDR2 SDRAM, RLDRAM II, and QDR II SRAM devices. High-speed serial interface channels with dynamic phase alignment (DPA) support data transfer at up to 1 Gbps using LVDS or HyperTransportTM technology I/O standards.
Figure2–1 shows an overview of the StratixII device.
Figure2–1.StratixII Block Diagram
M512 RAM Blocks for Dual-Port Memory, Shift Registers, & FIFO BuffersM4K RAM BlocksDSP Blocks forfor True Dual-Port Multiplication and FullMemory & Other EmbeddedImplementation of FIR FiltersMemory FunctionsIOEs Support DDR, PCI, PCI-X, SSTL-3, SSTL-2, HSTL-1, HSTL-2, LVDS, HyperTransport & otherI/O StandardsIOEsIOEsIOEsIOEsIOEsIOEsIOEsIOEsIOEsIOEsIOEsIOEsIOEsIOEsIOEsIOEsIOEsIOEsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsIOEsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsIOEsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsLABsIOEsLABsLABsLABsLABsLABsM-RAM BlockLABsLABsLABsDSPBlockStratix II Device Handbook, Volume 1
StratixII Architecture
Figure2–7.ALM in Normal ModeNote(1)
dataf0datae0datacdataadatabdataddatae1dataf14-InputLUTcombout0dataf0datae0datacdataadatab5-InputLUTcombout04-InputLUTcombout1dataddatae1dataf15-InputLUTcombout1dataf0datae0datacdataadatab5-InputLUTcombout0dataddatae1dataf1dataf0datae0dataadatabdatacdatad6-InputLUTcombout03-InputLUTcombout1dataf0datae0datacdataadatab5-InputLUTcombout0dataf0datae0dataadatabdatacdatad6-InputLUTcombout0dataddatae1dataf14-InputLUTcombout1datae1dataf16-InputLUTcombout1Note to Figure2–7:(1)
Combinations of functions with fewer inputs than those shown are also supported. For example, combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, etc.
The normal mode provides complete backward compatibility with four-input LUT architectures. Two independent functions of four inputs or less can be implemented in one StratixII ALM. In addition, a five-input function and an independent three-input function can be implemented without sharing inputs.
Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
For the packing of two five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab).
In the case of implementing two six-input functions in one ALM, four inputs must be shared and the combinational function must be the same. For example, a 4×2crossbar switch (two 4-to-1 multiplexers with
common inputs and unique select lines) can be implemented in one ALM, as shown in Figure2–8. The shared inputs are dataa, datab, datac, and datad, while the unique select lines are datae0 and dataf0 for function0, and datae1 and dataf1 for function1. This crossbar switch consumes four LUTs in a four-input LUT-based architecture.
Figure2–8.4 × 2 Crossbar Switch Example
4 × 2 Crossbar Switchsel0[1..0]inputainputbinputcinputdout1sel1[1..0]datae1dataf1Six-InputLUT(Function1)out0dataf0datae0dataadatabdatacdatadImplementation in 1 ALMSix-InputLUT(Function0)combout0combout1In a sparsely used device, functions that could be placed into one ALM may be implemented in separate ALMs. The QuartusII Compiler spreads a design out to achieve the best possible performance. As a device begins to fill up, the QuartusII software automatically utilizes the full potential of the StratixII ALM. The QuartusII Compiler automatically searches for functions of common inputs or completely independent functions to be placed into one ALM and to make efficient use of the device resources. In addition, you can manually control resource usage by setting location assignments.
Any six-input function can be implemented utilizing inputs dataa, datab, datac, datad, and either datae0 and dataf0 or datae1 and dataf1. If datae0 and dataf0 are utilized, the output is driven to register0, and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (see Figure2–9). If
Stratix II Device Handbook, Volume 1
StratixII Architecture
Stratix II Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP4SGX530HH35C2N中文规格书 - 图文
