DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Electrical Characteristics
Defense-grade Virtex?-5Q FPGAs are available in -2I, -1I, and -1M (only FX70T and FX100T devices in -1M) speed grades, with -2I having the highest performance. Virtex-5Q FPGA DC and AC characteristics are specified for the industrial temperature range. Except the operating
temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The
parameters included are common to popular designs and typical applications.
This Virtex-5Q FPGA data sheet, part of an overall set of documentation on the Virtex-5 family of FPGAs, is available on the Xilinx website:???
DS174, Virtex-5Q Family OverviewUG190, Virtex-5 FPGA User GuideUG191, Virtex-5 FPGA Configuration Guide
?????????
UG192, Virtex-5 FPGA System Monitor User GuideUG193, Virtex-5 FPGA XtremeDSP? DesignConsiderations User Guide
UG194, Virtex-5 FPGA Embedded Tri-Mode EthernetMAC User Guide
UG195, Virtex-5 FPGA Packaging and PinoutSpecification
UG196, Virtex-5 FPGA RocketIO? GTP TransceiverUser Guide
UG197, Virtex-5 FPGA Integrated Endpoint Block UserGuide for PCI Express? Designs
UG198, Virtex-5 FPGA RocketIO GTX TransceiverUser Guide
UG200, Embedded Processor Block in Virtex-5 FPGAsReference Guide
UG203, Virtex-5 FPGA PCB Designer’s Guide
All specifications are subject to change without notice.
Virtex-5Q FPGA DC Characteristics
Table 1:Absolute Maximum Ratings(1)
SymbolVCCINTVCCAUXVCCOVBATTVREF
Description
Internal supply voltage relative to GNDAuxiliary supply voltage relative to GNDOutput drivers supply voltage relative to GNDKey memory battery backup supplyInput reference voltage
3.3V I/O input voltage relative to GND(2) (user and dedicated I/Os)
3.3V I/O input voltage relative to GND (restricted to maximum of 100 user I/Os)(4)2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)
Range–0.5 to 1.1–0.5 to 3.0–0.5 to 3.75–0.5 to 4.05–0.5 to 3.75–0.75 to 4.05–0.85 to 4.3
(Industrial Temperature)
UnitsVVVVVVVVmAmAVV°C
VIN(3)
–0.75 to VCCO+0.5
±100±100–0.75 to 4.05–0.75 to VCCO+0.5
–65to150
IINVTSTSTG
Current applied to an I/O pin, powered or unpoweredTotal current applied to all I/O pins, powered or unpoweredVoltage applied to 3-state 3.3V output(2) (user and dedicated I/Os)Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os)Storage temperature (ambient)
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DCM Switching Characteristics
Table 76:Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
Symbol
Outputs Clocks (Low Frequency Mode)F1XLFMSMINF1XLFMSMAXF2XLFMSMINF2XLFMSMAXFDVLFMSMINFDVLFMSMAXFFXLFMSMINFFXLFMSMAX
CLKFX, CLKFX180CLKDV(5)
CLK2X, CLK2X180
CLK0, CLK90, CLK180, CLK270
32.00135.0064.00270.002.090.0032.00160.00
CLKIN (using DLL outputs)(1)(3)(4)CLKIN (using DFS outputs only)(2)(3)(4)PSCLK
32.00120.0064.00240.002.080.0032.00140.00
32.00120.0064.00240.002.080.0032.00140.00
MHzMHzMHzMHzMHzMHzMHzMHz
Description
Speed Grade-2I
-1I
-1M
Units
Input Clocks (Low Frequency Mode)FDLLLFMSMINFDLLLFMSMAXFCLKINLFFXMSMINFCLKINLFFXMSMAXFPSCLKLFMSMINFPSCLKLFMSMAX
32.00135.001.00160.001.00500.00
32.00120.001.00140.001.00450.00
32.00120.001.00140.001.00450.00
MHzMHzMHzMHzKHzMHz
Outputs Clocks (High Frequency Mode)F1XHFMSMINF1XHFMSMAXF2XHFMSMINF2XHFMSMAXFDVHFMSMINFDVHFMSMAXFFXHFMSMINFFXHFMSMAX
CLKFX, CLKFX180(5)CLKDV(5)
CLK2X, CLK2X180
CLK0, CLK90, CLK180, CLK270
120.00500.00240.00500.007.5333.34140.00375.00
CLKIN (using DLL outputs)(1)(3)(4)
CLKIN (using DFS outputs only)(2)(3)(4)(5)PSCLK
120.00450.00240.00450.007.5300.00140.00350.00
120.00450.00240.00450.007.5300.00140.00350.00
MHzMHzMHzMHzMHzMHzMHzMHz
Input Clocks (High Frequency Mode)FDLLHFMSMINFDLLHFMSMAXFCLKINHFFXMSMINFCLKINHFFXMSMAXFPSCLKHFMSMINFPSCLKHFMSMAXNotes:
1.2.3.4.5.
DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum inputfrequency.
When using a CLKIN frequency > 400MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55to 55/45).
Only available for I-temperature conditions.
120.00500.0025.00375.001.00500.00
120.00450.0025.00350.001.00450.00
120.00450.0025.00350.001.00450.00
MHzMHzMHzMHzKHzMHz
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 81:Miscellaneous Timing Parameters
Symbol
Time Required to Achieve LOCKTDLL_240TDLL_120_240TDLL_60_120TDLL_50_60TDLL_40_50TDLL_30_40TDLL_24_30TDLL_30TFX_MINTFX_MAX
TDLL_FINE_SHIFT
DLL output – Frequency range > 240MHz(1)DLL output – Frequency range 120 - 240MHz(1)DLL output – Frequency range 60 - 120MHz(1)DLL output – Frequency range 50 - 60MHz(1)DLL output – Frequency range 40 - 50MHz(1)DLL output – Frequency range 30 - 40MHz(1)DLL output – Frequency range 24 - 30MHz(1)DLL output – Frequency range < 30MHz(1)DFS outputs(2)
Multiplication factor for DLL lock time with Fine Shift
80.00250.00900.001300.002000.003600.005000.005000.0010.0010.002.00
80.00250.00900.001300.002000.003600.005000.005000.0010.0010.002.00
80.00250.00900.001300.002000.003600.005000.005000.0010.0010.002.00
μsμsμsμsμsμsμsμsmsms
Description
Speed Grade-2I
-1I
-1M
Units
Fine Phase ShiftingTRANGE_MSTRANGE_MR(3)
Absolute shifting range in maximum speed modeAbsolute shifting range in maximum range mode
7.0010.00
7.0010.00
7.0010.00
nsns
Delay LinesTTAP_MS_MINTTAP_MS_MAXTTAP_MR_MIN(3)TTAP_MR_MAX(3)Notes:
1.2.3.
Tap delay resolution (Min) in maximum speed modeTap delay resolution (Max) in maximum speed modeTap delay resolution (Min) in maximum range modeTap delay resolution (Max) in maximum range mode
7.0030.0010.0040.00
7.0030.0010.0040.00
7.0030.0010.0040.00
pspspsps
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.Maximum range is not available outside of I-temperature conditions.
Table 82:Frequency Synthesis
Attribute
CLKFX_MULTIPLYCLKFX_DIVIDE
Min21
Max3332
Table 83:DCM Switching Characteristics
Symbol
TDMCCK_PSEN/ TDMCKC_PSEN
TDMCCK_PSINCDEC/ TDMCKC_PSINCDECTDMCKO_PSDONE
Description
PSEN Setup/HoldPSINCDEC Setup/HoldClock to out of PSDONE
Speed Grade-2I1.350.001.350.001.12
-1I1.560.001.560.001.30
-1M1.560.001.560.001.30
Unitsnsnsns
DS714 (v2.2) January 17, 2011Product Specification
FPGA可编程逻辑器件芯片XC2S30-5FG256I中文规格书 - 图文
