CAS Latency (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 36 (page 80). CL isthe delay, in clock cycles, between the registration of a READ command and the availa-bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, dependingon the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not beused as an unknown operation otherwise incompatibility with future versions may re-sult.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-ture allows the READ command to be issued prior to tRCD (MIN) by delaying the inter-nal command to the DDR2 SDRAM by AL clocks. The AL feature is described in furtherdetail in Posted CAS Additive Latency (AL) (page 86).
Examples of CL = 3 and CL = 4 are shown in Figure 37; both assume AL = 0. If a READcommand is registered at clock edge n, and the CL is m clocks, the data will be availablenominally coincident with clock edge n + m (this assumes AL = 0).
Figure 37: CL
CK#CKCommandREADNOPNOPNOPNOPNOPNOPT0T1T2T3T4T5T6DQS, DQS#DQCL = 3 (AL = 0)DO nDO n + 1DO n + 2DO n + 3CK#CKCommandT0T1T2T3T4T5T6READNOPNOPNOPNOPNOPNOPDQS, DQS#DQCL = 4 (AL = 0)DO nDO n + 1DO n + 2DO n + 3Transitioning dataDon’t care
Notes:
1.BL = 4.
2.Posted CAS# additive latency (AL) = 0.
3.Shown with nominal tAC, tDQSCK, and tDQSQ.
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5.tQH is derived from tHP: tQH = tHP - tQHS.
6.The data valid window is derived for each DQS transition and is tQH - tDQSQ.7.DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
Figure 57: Data Output Timing – tAC and tDQSCK
T01CK#CK
tLZ (MIN)DQS#/DQS or
LDQS#/LDQS/UDQ#/UDQS3
DQ (last data valid)DQ (first data valid)All DQs collectively4
tLZ (MIN)T3T3T3T3nT3nT3nT4T4T4T4nT4nT4nT5T5T5T5nT5nT5nT6T6T6T6nT6nT6ntDQSCK2 (MIN)tDQSCK2 (MAX)tHZ (MAX)T1T2T3T3nT4T4nT5T5nT6T6nT7tRPREtRPSTtAC5 (MIN)tAC5 (MAX)tHZ (MAX)Notes:
1.READ command with CL = 3, AL = 0 issued at T0.
2.tDQSCK is the DQS output window relative to CK and is the long-term component of
DQS skew.
3.DQ transitioning after DQS transitions define tDQSQ window.
4.All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
5.tAC is the DQ output window relative to CK and is the “long term” component of DQskew.
6.tLZ (MIN) and tAC (MIN) are the first valid signal transitions.7.tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.
8.I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
WRITE
WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RLminus one clock cycle (WL = RL - 1CK) (see READ (page 78)). The starting column andbank addresses are provided with the WRITE command, and auto precharge is eitherenabled or disabled for that access. If auto precharge is enabled, the row being accessedis precharged at the completion of the burst.Note:
For the WRITE commands used in the following illustrations, auto precharge is disa-bled.
During WRITE bursts, the first valid data-in element will be registered on the first risingedge of DQS following the WRITE command, and subsequent data elements will be reg-istered on successive edges of DQS. The LOW state on DQS between the WRITE com-mand and the first rising edge is known as the write preamble; the LOW state on DQSfollowing the last data-in element is known as the write postamble.
The time between the WRITE command and the first rising DQS edge is WL ±tDQSS.Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as
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±tDQSS. tDQSS is specified with a relatively wide range (25% of one clock cycle). All ofthe WRITE diagrams show the nominal case, and where the two extreme cases (tDQSS[MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Figure 58(page 108) shows the nominal case and the extremes of tDQSS for BL = 4. Upon com-pletion of a burst, assuming no other commands have been initiated, the DQ will re-main High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command toprovide continuous flow of input data. The first data element from the new burst is ap-plied after the last element of a completed burst. The new WRITE command should beissued x cycles after the first WRITE command, where x equals BL/2.
Figure 59 (page 109) shows concatenated bursts of BL = 4 and how full-speed randomwrite accesses within a page or pages can be performed. An example of nonconsecutiveWRITEs is shown in Figure 60 (page 109). DDR2 SDRAM supports concurrent auto pre-charge options, as shown in Table 43.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4operation. Once the BL = 4 WRITE command is registered, it must be allowed to com-plete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto pre-charge disabled) might be interrupted and truncated only by another WRITE burst aslong as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architectureof DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncatedwith any command except another WRITE command, as shown in Figure 61(page 110).
Data for any WRITE burst may be followed by a subsequent READ command. To followa WRITE, tWTR should be met, as shown in Figure 62 (page 111). The number of clockcycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for anyWRITE burst may be followed by a subsequent PRECHARGE command. tWR must bemet, as shown in Figure 63 (page 112). tWR starts at the end of the data burst, regardlessof the data mask condition.
Table 43: WRITE Using Concurrent Auto Precharge
From Command(Bank n)WRITE with auto prechargeTo Command(Bank m)READ or READ with auto prechargeWRITE or WRITE with auto prechargePRECHARGE or ACTIVATEMinimum Delay(with Concurrent Auto Precharge)(CL - 1) + (BL/2) + tWTR(BL/2)1UnitstCKtCKtCKPDF: 09005aef8565148a
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Figure 61: WRITE Interrupted by WRITE
T0T1T2T3T4T5T6T7T8T9CK#CKCommandAddress
A10
DQS, DQS#
DQ
WRITE1 aNOP2WRITE3 bNOP2NOP2NOP2NOP2Valid4Valid4Valid4Valid5Valid5Valid677777DI aDI a + 1DIa + 2DIa + 3DIbDIb + 1DIb + 2DIb + 3DIb + 4DIb + 5DIb + 6DIb + 7WL = 32-clock requirementWL = 3PDF: 09005aef8565148a
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Figure 62: WRITE-to-READ
T0
T1
T2
T2n
T3
T3n
T4
T5
T6
T7
T8
T9
T9n
CK#CKCommandWRITEBank a,Col bNOPNOPNOPNOPNOPtWTR1READBank a,Col nNOPNOPNOPAddresstDQSS (NOM)DQS, DQS#DQDMtDQSS (MIN)DQS, DQS#DQDMtDQSS (MAX)DQS, DQS#DQDMWL ± tDQSS2CL = 3DIbDIWL - tDQSS2CL = 3DIbDIWL + tDQSS2CL = 3DIbDITransitioning DataDon’t Care
Notes:
1.tWTR is required for any READ following a WRITE to the same device, but it is not re-quired between module ranks.
2.Subsequent rising DQS signals must align to the clock within tDQSS.3.DI b = data-in for column b; DO n = data-out from column n.4.BL = 4, AL = 0, CL = 3; thus, WL = 2.
5.One subsequent element of data-in is applied in the programmed order following DI b.6.tWTR is referenced from the first positive CK edge after the last data-in pair.7.A10 is LOW with the WRITE command (auto precharge is disabled).
8.The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is
greater.
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MEMORY存储芯片PC28F128J3F75A中文规格书 - 图文
