Figure 19.Figure 20.
Note: 2.Intel Agilex I/O Features and Usage
UG-20244 | 2024.04.05
Simplified View of Single-Ended GPIO Input Path
aclr / sclraset / ssetHRdout[3]AFRDDIOINdout[2]2DelayPadDDIOElementINdout[1]DDIOINB1dout[0]3ck_hrck_fr1.The pad receives data.
2.DDIO IN (1) captures data on the rising and falling edges of ck_fr and sends thedata, signals (A) and (B) in the following waveform figure, at single data rate.3.DDIO IN (2) and DDIO IN (3) halve the data rate.
4.
dout[3:0] presents the data as a half-rate bus.
Input Path Waveform in DDIO Mode with Half-Rate Conversion
In this figure, the data goes from full-rate clock at double data rate to half-rate clock at single data rate. Thedata rate is divided by four and the bus size is increased by the same ratio. The overall throughput through theGPIO IP remains unchanged.
The actual timing relationship between different signals may vary depending on the specific design, delays, andphases that you choose for the full-rate and half-rate clocks.
padD0D1D2D3D4D5D6D7ck_fr(A)D0D2D4D6(B)D1D3D5D7ck_hrdout[0]D0D4dout[1]D1D5dout[2]D2D6dout[3]D3D7The GPIO IP does not support dynamic calibration of bidirectional pins.Related Information
GPIO Intel FPGA IP Parameter Settings on page 27
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2.Intel Agilex I/O Features and UsageUG-20244 | 2024.04.05
Output and Output Enable Paths
The output delay element sends data to the pad through the output buffer.Each output path contains two stages of DDIOs, which are half-rate and full-rate.
Figure 21.
Simplified View of Single-Ended GPIO Output Path
from OutputEnable Path
oe
aclr / sclraset / sset
HRdin[0]din[2]
DDIOOUTdin[1]din[3]ck_hrck_fr
Figure 22.
Output Path Waveform in DDIO Mode with Half-Rate Conversion
ck_hrdin[0]din[1]din[2]din[3](A)(B)ck_frPad010101010101010000011101001101001010011001100101AFRDDIOOUTDelayElementPadDDIOOUTBFigure 23.Simplified View of Output Enable Path
aclr / sclraset / ssetHRoe[1]oe[0]ck_hrck_frDDIOOUTFRFFDelayElementFrom OutputData PathSend Feedback
FPGA可编程逻辑器件芯片EP3C10U256I6中文规格书
