Configuration Register
Read Configuration Register
The read configuration register (RCR) is a 16-bit read/write register used to select busread mode (synchronous or asynchronous) and to configure device synchronous burstread characteristics. To modify RCR settings, use the CONFIGURE READ CONFIGURA-TION REGISTER command. RCR contents can be examined using the READ DEVICEIDENTIFIER command and then reading from offset 0x05. On power-up or exit from re-set, the RCR defaults to asynchronous mode. RCR bits are described in more detail be-low.
Note: Reading the configuration register is a nonarray READ operation. When the oper-ation occurs in asynchronous page mode, only the first data is valid, and all subsequentdata are undefined. When the operation occurs in synchronous burst mode, the sameword of data requested will be output on successive clock edges until the burst lengthrequirements are satisfied.
Table 17: Read Configuration Register
Bits15NameRead mode (RM)Settings/Description0 = Synchronous burst mode read1 = Asynchronous page mode read (default)0000 = Code 0 (reserved)0001 = Code 1 (reserved)0010 = Code 20011 = Code 30100 = Code 40101 = Code 50110 = Code 60111 = Code 71000 = Code 81001 = Code 91010 = Code 101011 = Code111100 = Code 121101 = Code 131110 = Code 141111 = Code 15 (default)14:11Latency count(LC[3:0])1098765:432:0WAIT polarity (WP)Reserved (R)WAIT delay (WD)Burst sequence (BS)Clock edge (CE)Reserved (R)Burst wrap (BW)0 = WAIT signal is active LOW (default)1 = WAIT signal is active HIGHDefault 0, Nonchangeable0 = WAIT de-asserted with valid data1 = WAIT de-asserted one data cycle before valid data (default)Default 0, Nonchangeable0 = Falling edge1 = Rising edge (default)Default 0, Nonchangeable0 = Wrap; Burst accesses wrap within burst length set by BL[2:0]1 = No Wrap; Burst accesses do not wrap within burst length (default)011 = 16-word burst111 = Continuous burst (default)(Other bit settings are reserved)Burst length (BL[2:0])001 = 4-word burst010 = 8-word burstRead Mode
The read mode (RM) bit selects synchronous burst mode or asynchronous page modeoperation for the device. When the RM bit is set, asynchronous page mode is selected(default). When RM is cleared, synchronous burst mode is selected.
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p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
256Mb and 512Mb (256Mb/256Mb), P30-65nm
Common Flash Interface
Table 34: Partition Region 1: Partition and Erase Block Map Information
256MbAddress12D:12E:12F:130:131:132:133:134:135:136:137:138:139:13A:13B:13C:13D:13E:13F:140:141:142:143:144:145:146:147:148:149:14A:14B:14C:14D:14E:14F:150:151:Bottom- -01- -24- -00- -01- -00- -11- -00- -00- -02- -03- -00- -80- -00- -64- -00- -02- -03- -00- -80- -00- -00- -00- -80- -FE- -00- -00- -02- -64- -00- -02- -03- -00- -80- -00- -00- -00- -80Top- -01- -24- -00- -01- -00- -11- -00- -00- -02- -FE- -00- -00- -02- -64- -00- -02- -03- -00- -80- -00- -00- -00- -80- -03- -00- -80- -00- -64- -00- -02- -03- -00- -80- -00- -00- -00- -80PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
256Mb and 512Mb (256Mb/256Mb), P30-65nm
Flowcharts
Figure 19: Buffered Enhanced Factory Programming (BEFP) Procedure
Setup Phase
StartProgram and Verify Phase
Read statusregisterExit PhaseRead statusregisterIssue BEFP SETUPData = 0x80Issue BEFP CONFIRMData = 00D0hBuffer ready?No (SR0 = 1)BEFP exited?No (SR7 = 0)Yes (SR0 = 0)Write data word to bufferYes (SR7 = 1)Full statusregister checkfor errorsBEFP setupdelayBuffer full?Read statusregisterYesRead statusregisterBEFP setupdone?Yes (SR7 = 0)Programdone?NoFinishNo (SR0 = 1)No (SR7 = 1)SR error-handleruser-definedYesExitYes (SR0 = 0)Programmore data?NoWrite 0xFFFFoutside blockPDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
256Mb and 512Mb (256Mb/256Mb), P30-65nm
Flowcharts
Figure 25: Status Register Procedure
StartCommand Cycle-Issue STATUS REGISTER command-Address = any device address-Data = 0x70Data Cycle-Read Status Register SR[7:0]SR7 = 1YesSet/Resetby deviceNoSR6 = 1NoYesErase SuspendSee Suspend/Resume FlowchartSR2 = 1NoYesProgram SuspendSee Suspend/Resume FlowchartSR5 = 1YesSR4 = 1YesErrorErase failureNoErrorCommandsequenceNo-Set by device-Reset by user-See Clear StatusRegister CommandYesSR4 = 1NoErrorProgram failureSR3 = 1NoSR1 = 1NoEndYesErrorVPEN/VPP p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN 256Mb and 512Mb (256Mb/256Mb), P30-65nmMaximum Ratings and Operating Conditions Maximum Ratings and Operating Conditions Stresses greater than those listed can cause permanent damage to the device. This isstress rating only, and functional operation of the device at these or any other condi-tions above those indicated is not guaranteed. Table 38: Maximum Ratings ParameterTemperature under biasStorage temperatureVoltage on any signal (except VCC, VPP, and VCCQ)VPP voltageVCC voltageVCCQ voltageOutput short circuit currentMaximum Rating–40°C to + 85 °C–65°C to + 125 °C–2V to +4V–2V to +11.5V–2V to +4V–2V to +5.6V100mA11, 2113NotesPDF: 09005aef84566799 p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
MEMORY存储芯片PC28F512P33TFA中文规格书 - 图文
