DLL Enable/Disable
The DLL may be enabled or disabled by programming bit E0 during the LM command,as shown in Figure 38 (page 84). These specifications are applicable when the DLL is en-abled for normal operation. DLL enable is required during power-up initialization andupon returning to normal operation after having disabled the DLL for the purpose ofdebugging or evaluation. Enabling the DLL should always be followed by resetting theDLL using the LM command.
The DLL is automatically disabled when entering SELF REFRESH operation and is auto-matically re-enabled and reset upon exit of SELF REFRESH operation.
Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur be-fore a READ command can be issued to allow time for the internal clock to synchronizewith the external clock. Failing to wait for synchronization to occur may result in a vio-lation of the tAC or tDQSCK parameters.
Anytime the DLL is disabled and the device is operated below 25 MHz, any AUTO RE-FRESH command should be followed by a PRECHARGE ALL command.
Output Drive Strength
The output drive strength is defined by bit E1, as shown in Figure 38. The normal drivestrength for all outputs is specified to be SSTL_18. Programming bit E1 = 0 selects nor-mal (full strength) drive strength for all outputs. Selecting a reduced drive strength op-tion (E1 = 1) will reduce all outputs to approximately 45 to 60 percent of the SSTL_18drive strength. This option is intended for the support of lighter load and/or point-to-point environments.
DQS# Enable/Disable
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the dif-ferential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a single-ended mode and the DQS# ball is disabled. When disabled, DQS# should be left float-ing; however, it may be tied to ground via a 20Ω to 10kΩ resistor. This function is alsoused to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 =0), then both DQS# and RDQS# will be enabled.
RDQS Enable/Disable
The RDQS ball is enabled by bit E11, as shown in Figure 38. This feature is only applica-ble to the x8 configuration. When enabled (E11 = 1), RDQS is identical in function andtiming to data strobe DQS during a READ. During a WRITE operation, RDQS is ignoredby the DDR2 SDRAM.
Output Enable/Disable
The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 38. When ena-bled (E12 = 0), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) function normally. Whendisabled (E12 = 1), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) are disabled, thus re-moving output buffer current. The output disable feature is intended to be used duringIDD characterization of read current.
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
Preliminary
1Gb: x4, x8, x16 DDR2 SDRAM
READ
Figure 54: Bank Read – with Auto Precharge
T0T1tCKT2tCHtCLT3T4T5T6T7T7nT8T8nCK#CKCKECommand1NOP1ACTNOP1READ2,3NOP1NOP1NOP1NOP1NOP1ACTAddressRACol n4RAA10RARABank addressBank xBank xAL = 1tRCDtRAStRCtRTPtRPCL = 3Bank xDMCase 1: tAC (MIN) and tDQSCK (MIN)DQS, DQS#tLZ (MIN)DQ6tDQSCK (MIN)5tRPREtRPST5DO ntLZ (MIN)tAC (MIN)tDQSCK (MAX) tHZ (MIN)Case 2: tAC (MAX) and tDQSCK (MAX) DQS, DQS#tLZ (MAX) DQ64-bitprefetch
5tRPREtRPST5DO ntInternalLZ (MAX)precharge
tAC (MAX)tHZ (MAX)Transitioning DataDon’t Care
Notes:
1.NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2.BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.
3.The DDR2 SDRAM internally delays auto precharge until both tRAS (MIN) and tRTP (MIN)
have been satisfied.4.Enable auto precharge.
5.I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,but to when the device begins to drive or no longer drives, respectively.
6.DO n = data-out from column n; subsequent elements are applied in the programmedorder.
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
Preliminary
1Gb: x4, x8, x16 DDR2 SDRAM
READ
Figure 55: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window
T1
T2
T2n
T3
T3n
T4
CK#CK
tHP1tHP1tDQSQ2tHP1tHP1tDQSQ2tHP1tDQSQ2tHP1tDQSQ2DQS#DQS3
DQ (last data valid)DQ4DQ4DQ4DQ4DQ4DQ4DQ (first data no longer valid)tQH5tQH5tQHS tQH5tQHStQH5tQHS tQHS DQ (last data valid)DQ (first data no longer valid)T2T2T2nT2nT3T3T3nT3nAll DQs and DQS collectively6Earliest signal transitionLatest signal transitionT2T2nT3T3nData valid windowDatavalid windowDatavalid windowDatavalid window
Notes:
1.tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.
2.tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
3.DQ transitioning after the DQS transition defines the tDQSQ window. DQS transitions at
T2 and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”4.DQ0, DQ1, DQ2, DQ3 for x4 or DQ[7:0] for x8.5.tQH is derived from tHP: tQH = tHP - tQHS.
6.The data valid window is derived for each DQS transition and is defined as tQH - tDQSQ.
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
Preliminary
1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 75: REFRESH Command-to-Power-Down Entry
CK#CK
Command
ValidREFRESHNOPtCKE (MIN)CKE
1 x tCKPower-down1entry
Don’t Care
T0T1T2T3Note:
1.The earliest precharge power-down entry may occur is at T2, which is 1 × tCK after the
REFRESH command. Precharge power-down entry occurs prior to tRFC (MIN) being satis-fied.
Figure 76: ACTIVATE Command-to-Power-Down Entry
CK#CK
Command
ValidACTNOPT0T1T2T3Address
VALIDtCKE (MIN)CKE
1 tCKPower-down1entry
Don’t Care
Note:
1.The earliest active power-down entry may occur is at T2, which is 1 × tCK after the ACTI-VATE command. Active power-down entry occurs prior to tRCD (MIN) being satisfied.
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
Preliminary
1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 77: PRECHARGE Command-to-Power-Down Entry
CK#CK
Command
ValidPRENOPT0T1T2T3Address
A10
ValidAll banks vsSingle banktCKE (MIN)CKE
1 x tCKPower-down1
entry
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
MEMORY存储芯片ADM3232EARNZ中文规格书 - 图文
