Flip-Flops with Clear?Synchronous Clearmodule flipflop(D, Clock, Resetn, Q);input D, Clock, Resetn;output Q;regQ;always @(posedgeClock)if (!Resetn)// check value of reset on clock edgeQ <= 0;else Q <= D;endmoduleFebruary 15, 2012ECE 152A -Digital Design Principles264-Bit Binary Counter?Counter includes reset and enablemodule upcount(Resetn, Clock, E, Q);input Resetn, Clock, E;output [3:0] Q;reg[3:0] Q;always @(negedgeResetnor posedgeClock)if (!Resetn)Q <= 0; // asynchronous reset overrides enable else if (E)Q <= Q + 1; // synthesizes adder circuitendmoduleFebruary 15, 2012ECE 152A -Digital Design Principles274-Bit Binary Counter?Functional SimulationasynchronousresetenablecountresetenableFebruary 15, 2012ECE 152A -Digital Design Principles28Finite State Machine (FSM) Design?Recall state diagram for JK flip-flop counter from previous lecture100111000011010February 15, 2012ECE 152A -Digital Design Principles29Finite State Machine (FSM) Design?The State TablePSA00001111B00110011C01010101A+1X001XX0NSB+0X101XX1C+0X101XX0February 15, 2012ECE 152A -Digital Design Principles30
电子电路 L8- Sequential Circuit Design with Verilog(1) - 图文
