电子电路 L8- Sequential Circuit Design with Verilog(1) - 图文 

The Edge Triggered T Flip-Flop?Assign characteristic function to Q on rising clock edge (Q+= T XOR Q)module Tflipflop(T, Clock, Q);input T, Clock;output Q;regQ;always @(posedgeClock)Q = T ^ Q; // Q = T XOR QendmoduleFebruary 15, 2012ECE 152A -Digital Design Principles11The Edge Triggered T Flip-Flop?Functional SimulationholdtoggleholdtoggletoggleholdFebruary 15, 2012ECE 152A -Digital Design Principles12Blocking and Non-Blocking Assignments?Q = D?Equal sign (=) signifies a blocking assignment?Statements are evaluated in the order in which they are written?If a variable is given a value by a blocking assignment, the new value is used in evaluating all subsequent statements in the blockFebruary 15, 2012ECE 152A -Digital Design Principles13Blocking and Non-Blocking Assignments?Blocking Assignment Statement Examplemodule example1(D, Clock, Q1, Q2);input D, Clock;output Q1, Q2;regQ1, Q2;always @(posedgeClock)beginQ1 = D;Q2 = Q1;endendmoduleFebruary 15, 2012ECE 152A -Digital Design Principles14Blocking and Non-Blocking Assignments?Example synthesizes two positive edge triggered D flip-flops?Both flip-flops triggered by same clock edge?Both assignments in always block are blocking??Q1 gets the value DQ2 then gets the new value of Q1?Q1+, which is now DFebruary 15, 2012ECE 152A -Digital Design Principles15