Sequential Circuit Design with VerilogECE 152A –Winter 2012Reading Assignment?Brown and Vranesic?6 Combinational –Circuit Building Blocks?6.6 Verilog for Combinational Circuits???6.6.1 The Conditional Operator6.6.2 The If-Else Statement6.6.3 The Case StatementFebruary 15, 2012ECE 152A -Digital Design Principles2Reading Assignment?Brown and Vranesic(cont)?7 Flip-Flops, Registers, Counters, and a Simple Processor?7.12 Using Storage Elements with CAD Tools?????7.12.2 Using Verilog Constructs for Storage Elements7.12.3 Blocking and Non-Blocking Assignments7.12.4 Non-Blocking Assignments for Combinational Circuits7.12.5 Flip-Flops with Clear Capability7.13.3 Using Verilog Constructs for Registers and CountersECE 152A -Digital Design Principles37.13 Using Registers and Counters with CAD Tools?February 15, 2012The Gated D Latch?Transparent on high phase of clockmodule D_latch(D, Clk, Q);input D, Clk;output Q;regQ;always @(D or Clk)if (Clk)Q = D;endmoduleFebruary 15, 2012ECE 152A -Digital Design Principles4The Gated D Latch?The “if”construct?When D or CLK change value: ?if CLK = 1, set Q = D?Since there is no else, assignment occurs only when CLK = 1??Q follows D when CLK = 1Q remains latched on CLK = 0?“Always”construct triggered by change in value of D or CLK ?Either change can cause the output to changeECE 152A -Digital Design Principles5February 15, 2012
电子电路 L8- Sequential Circuit Design with Verilog(1) - 图文
