Table1–31 lists the transceiver jitter specifications for protocols supported by StratixIVGT devices.
Table1–31.Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 1 of 2)Symbol/Description
Conditions
–1 Industrial Speed –2 Industrial Speed –3 Industrial Speed
GradeGradeGradeMin
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
XLAUI/CAUI Transmit Jitter Generation (1), (3)Total Jitter
Pattern = PRBS-31VOD = 800 mV
Deterministic
Jitter
REFCLK = 644.53MHz4 (XLAUI)/
10 (CAUI) channels in Basic ×1 mode
—
—
0.17
—
—
0.17
—
—
0.17
UI
—
—
0.30
—
—
0.30
—
—
0.30
UI
XLAUI/CAUI Receiver Jitter Tolerance (1)Total Jitter tolerance
Pattern = PRBS-31Jitter Frequency = 40KHzPattern = PRBS-31 Equalization = Disabled
Sinusoidal Jitter tolerance
BER = 1E-12
Jitter Frequency ?4MHzPattern = PRBS-31Equalization = DisabledBER = 1E-12
XFI Transmitter Jitter Generation (2), (3)
Pattern = PRBS-31
Total jitter at 10.3125 Gbps
Vod = 800 mVREFCLK = 644.53 MHz
10 channels in Basic ×1 mode
OTL 4.10 (1), (3)Total Jitter at 11.18GbpsDeterministic Jitter
Pattern = PRBS-31VOD = 800 mVREFCLK = 698.75MHz
—
—
0.17
—
—
0.17
—
—
0.17
UI
—
—
0.30
—
—
0.30
—
—
0.30
UI
—
—
0.3
—
—
0.3
—
—
—
UI
>0.05
>0.05
—
UI
>5
>5
—
UI
>0.62
>0.62
—
UI
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table1–31.Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 2 of 2)Symbol/Description
Conditions
Jitter Frequency = 40KHzPattern = PRBS-31 Equalization = Disabled
Sinusoidal Jitter tolerance
BER = 1E-12
Jitter Frequency ?4MHzPattern = PRBS-31Equalization = DisabledBER = 1E-12
>0.05
>0.05
—
UI
>5
>5
—
UI
–1 Industrial Speed –2 Industrial Speed –3 Industrial Speed
GradeGradeGradeMin
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV DevicesSwitching Characteristics
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
PLL Specifications
Table1–34 lists the Stratix IV PLL specifications when operating in the commercial (0°to 85°C), industrial (–40° to 100°C), and military (–55°C to 125°C) junction temperature ranges.
Table1–34.PLL Specifications for Stratix IV Devices(Part 1 of 2)
SymbolfINfINPFDfVCO (2)tEINDUTY
Parameter
Input clock frequency (–2/–2x speed grade)Input clock frequency (–3 speed grade)Input clock frequency (–4 speed grade)Input frequency to the PFD
PLL VCO operating range (–2 speed grade)PLL VCO operating range (–3 speed grade)PLL VCO operating range (–4 speed grade)
Input clock or external feedback clock input duty cycleOutput frequency for internal global or regional clock (–2/–2x speed grade)
fOUT
Output frequency for internal global or regional clock (–3speed grade)
Output frequency for internal global or regional clock (–4speed grade)
Output frequency for external clock output (–2 speed grade)
fOUT_EXTtOUTDUTYtFCOMPtCONFIGPLLtCONFIGPHASEfSCANCLKtLOCKtDLOCK
Output frequency for external clock output (–3 speed grade)Output frequency for external clock output (–4 speed grade)Duty cycle for external clock output (when set to 50%)External feedback clock compensation timeTime required to reconfigure scan chainTime required to reconfigure phase shiftscanclk frequency
Time required to lock from end-of-device configuration or de-assertion of areset
Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays)PLL closed-loop low bandwidth
fCLBWtPLL_PSERRtARESETtINCCJ (4), (5)tOUTPJ_DC (6)
PLL closed-loop medium bandwidth PLL closed-loop high bandwidth (8)Accuracy of PLL phase shift
Minimum pulse width on the areset signalInput clock cycle to cycle jitter (FREF ≥ 100MHz)Input clock cycle to cycle jitter (FREF < 100MHz)Period Jitter for dedicated clock output (FOUT ≥ 100MHz)Period Jitter for dedicated clock output (FOUT < 100MHz)
Min555560060060040——————45——————————10————
Typ——————————————50—3.51———0.31.54——————
Max800 (1)717 (1)717 (1)32516001300130060800 (3)717 (3)717 (3)800 (3)717 (3)717 (3)5510——10011———±50—0.15±75017517.5
UnitMHzMHzMHzMHzMHzMHzMHz%MHzMHzMHzMHzMHzMHz%nsscanclk cyclesscanclk cyclesMHzmsmsMHzMHzMHzpsnsUI (p-p)ps (p-p)ps (p-p)mUI (p-p)
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV DevicesSwitching Characteristics
Table1–34.PLL Specifications for Stratix IV Devices(Part 2 of 2)
Symbol
Parameter
Cycle to Cycle Jitter for dedicated clock output (FOUT ≥100MHz)
Cycle to Cycle Jitter for dedicated clock output(FOUT <100MHz)
Period Jitter for clock output on regular I/O (FOUT ≥100MHz)
Period Jitter for clock output on regular I/O (FOUT <100MHz) (6),
Cycle to Cycle Jitter for clock output on regular I/O (FOUT ≥100MHz)
Cycle to Cycle Jitter for clock output on regular I/O (FOUT <100MHz)
Min—————————
Typ—————————
Max17517.5600606006025025±10
Unitps (p-p)mUI (p-p)ps (p-p)mUI (p-p)ps (p-p)mUI (p-p)ps (p-p)mUI (p-p)
%
tOUTCCJ_DC (6)
tOUTPJ_IO (6),
(9)
tOUTCCJ_IO
(9)
Period Jitter for dedicated clock output in cascaded PLLs
tCASC_OUTPJ_DC (FOUT ≥100MHz)(6), (7)
Period Jitter for dedicated clock output in cascaded PLLs (FOUT < 100MHz)fDRIFT
Frequency drift after PFDENA is disabled for duration of 100us
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
FPGA可编程逻辑器件芯片EP4SGX110HF35C2N中文规格书 - 图文
