Chapter4
User Primitives
The configuration primitives described in this chapter are provided for users to access FPGA configuration resources during or after FPGA configuration. For additional
information and instantiation templates, refer to UG615, Spartan-6 Libraries Guide for HDL Designs.
BSCAN_SPARTAN6
JTAG is a standard four-pin interface: TCK, TMS, TDI, and TDO. Many applications are built around this interface. The JTAG TAP controller is a dedicated state machine inside the configuration logic. BSCAN_SPARTAN6 provides access between the JTAG TAP controller and user logic in fabric. There are up to four instances of BSCAN_SPARTAN6 for each device. Each instance of this design element can handle one JTAG USER instruction
(USER1 through USER4) as set with the JTAG_CHAIN attribute. To handle all four USER instructions, four of these elements can be instantiated, and the JTAG_CHAIN attribute must be set appropriately. Table4-1 lists the BSCAN_SPARTAN6 port descriptions. Table 4-1:BSCAN_SPARTAN6 Port DescriptionsSignal Name SEL
TypeOutput
Function
Active-High interface selection output. SEL=1 when the JTAG instruction register holds the corresponding (USER1, USER2, USER3, or USER4) instruction. Change in Update_IR state. SEL changes on the falling edge of TCK in the UPDATE_IR state of the TAP controller.
Active-High reset output. RESET=1 during the TEST-LOGIC-RESET state, PROGRAM_B, or during
power-up. This signal is deasserted on the falling edge of TCK.Fed through directly from the FPGA TDI pin.
DRCK is the same as TCK in the Capture_DR and Shift_DR states. If the interface is not selected by the instruction register, DRCK remains High.
Active-High pulse indicating the Capture_DR state. This signal is asserted on the falling edge of TCK.
Active-High pulse indicating the Update_DR state. This signal is asserted on the falling edge of TCK.
Active-High pulse indicating the Shift_DR state. This signal is asserted on the falling edge of TCK. Indicates JTAG is in Run Test/Idle state.
RESETOutput
TDIDRCK
OutputOutput
CAPTUREUPDATESHIFTRUNTEST
OutputOutputOutputOutput
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Chapter 2:Configuration Interface Basics
RDWR_B
RDWR_B is an input to the Spartan-6 device that controls whether the data pins are inputs or outputs:
? IfRDWR_B =0, the data pins are inputs (writing to the FPGA).? IfRDWR_B =1, the data pins are outputs (reading from the FPGA).
For configuration, RDWR_B must be set for write control (RDWR_B=0). For readback, RDWR_B must be set for read control (RDWR_B=1) while CSI_B is deasserted. (For details, refer to Chapter6, Readback and Configuration Verification.) If readback is not needed, RDWR_B can be tied to ground or used for debugging with SelectMAP ABORT.The RDWR_B signal is ignored while CSI_B is deasserted. Read/write control of the 3-stating of the data pins is asynchronous. The FPGA actively drives SelectMAP datawithout regard to CCLK if RDWR_B is set for read control (RDWR_B=1, Readback) whileCSI_B is asserted. If RDWR_B is changed while CSI_B is still asserted, the FPGA
asynchronously detects the violation and drives the BUSY signal, indicating an ABORT.The status register is not updated until the next rising CCLK edge (see SelectMAP ABORT,page157).
CCLK
All activity on the SelectMAP data bus is synchronous to CCLK. When RDWR_B is set for write control (RDWR_B=0, Configuration), the FPGA samples the SelectMAP data pins on rising CCLK edges. When RDWR_B is set for read control (RDWR_B=1, Readback), the FPGA updates the SelectMAP data pins on rising CCLK edges.
In Slave SelectMAP mode, configuration can be paused by stopping CCLK (see Non-Continuous SelectMAP Data Loading, page37).
Continuous SelectMAP Data Loading
Continuous data loading is used in applications where the configuration controller can provide an uninterrupted stream of configuration data. After power-up, the configuration controller sets the RDWR_B signal for write control (RDWR_B=0) and asserts the CSI_B signal (CSI_B=0), causing the device to drive BUSY Low (this transition is asynchronous). RDWR_B must be driven Low before CSI_B is asserted, otherwise an ABORT occurs, see SelectMAP ABORT, page157.
On the next rising CCLK edge, the device begins sampling the data pins. Pins D[0:15] are sampled by Configuration until the bus width is determined. See Sync Word/Bus Width Auto Detection, page78 for details. After bus width is determined, the proper width of the data bus is sampled for the synchronization word search. Configuration begins after the synchronization word is clocked into the device.
After the configuration bitstream is loaded, the device enters the startup sequence. The device asserts its DONE signal High in the phase of the startup sequence that is specified by the bitstream (see Startup (Step8) in Chapter5). The configuration controller should continue sending CCLK pulses until after the startup sequence has finished. (This can require several CCLK pulses after DONE goes High. See Startup (Step8) in Chapter5 for details).
After configuration, the CSI_B and RDWR_B signals can be deasserted, or they can remain asserted. Because the SelectMAP port is inactive, toggling RDWR_B at this time does not cause an abort. Figure2-8 summarizes the timing of SelectMAP configuration with continuous data loading.
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Chapter 4:User Primitives
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2024
Chapter 5:Configuration Details
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2024
eFUSE
After configuration, the device cannot be reconfigured without toggling the PROGRAM_B pin, cycling power, or issuing the JPROGRAM instruction. Fallback reconfiguration and IPROG reconfiguration (see Fallback MultiBoot, page134) are disabled after encryption is turned on. Readback is available through the ICAP primitive (see Bitstream Encryption and Internal Configuration Access Port (ICAP)). None of these events resets the key if VBATT or VCCAUX is maintained.
A mismatch between the key used to generate the encrypted bitstream and the key stored in the device causes configuration to fail with the INIT_B pin going Low and the DONE pin remaining Low.
Bitstream Encryption and Internal Configuration Access Port (ICAP)
The Internal Configuration Access Port (ICAP) primitive provides the user logic with access to the Spartan-6 FPGA configuration interface. The ICAP interface is similar to the SelectMAP interface, although the restrictions on readback for the SelectMAP interface do not apply to the ICAP interface after configuration. Users can perform readback through the ICAP interface even if bitstream encryption is used. Unless the designer wires the ICAP interface to user I/O, this interface does not offer attackers a method for defeating the Spartan-6 FPGA AES encryption scheme.
Users concerned about the security of their design should not:?-or-?
Instantiate the ICAP primitive.
Like the other configuration interfaces, the ICAP interface does not provide access to the key register.
Wire the ICAP interface to user I/O
VBATT
The encryption key memory cells are volatile and must receive continuous power to retain their contents. During normal operation, these memory cells are powered by the auxiliary voltage input (VCCAUX), although a separate VBATT power input is provided for retaining the key when VCCAUX is removed. Because VBATT draws very little current (on the order of nanoamperes), a small watch battery is suitable for this supply. (To estimate the battery life, refer to VBATT DC Characteristics in the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics and the battery specifications.) At less than a 150nA load, the endurance of the battery should be limited only by its shelf life.
VBATT does not draw any current and can be removed while VCCAUX is applied. VBATT cannot be used for any purpose other than retaining the encryption keys when VCCAUX is removed.
eFUSE
The fuse link is programmed by flowing a large current for a specific amount of time. Fuse programming current is provided by a fixed external voltage supply (VFS pin). The maximum level is controlled by an internally generated supply. eFUSEs are one-time programmable.
The resistance of a programmed fuse link is typically a few orders of magnitude higher than that of a pristine one. A programmed fuse is assigned a logic value of 1 and a pristine fuse 0.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
FPGA可编程逻辑器件芯片XC2S150-6FG456I中文规格书 - 图文
