出处：Lee H H, Park W H, Ryu H G. High speed digital hybrid PLL frequency synthesizer[C]// Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings. 2006.
锁相技术译文翻译
英文原名：High Speed Digital Hybrid PLL Frequency
Synthesizer
译文：高速数字混合锁相环频率合成器 年纪专业： 通信工程
姓名： 学号：
2011年 5月2日
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英文 High Speed Digital Hybrid PLL Frequency Synthesizer Abstract：The conventional PLL(Phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL (DH-PLL) which includes the open loop structure into the conventional PLL synthesizer has been studied to overcome this problem. It operates in high speed, but the hardware complexity and power consumption are other serious problems since the DLT (digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO (voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit makes the negligible overshoot and much shorter settling time for the ultra fast switching speed. Also, the hardware complexity and power consumption get decreased to about 28%, compared with the conventional DH-PLL. Key Words: PLL, DLT, Frequency synthesis I. INTRODUCTION High speed frequency synthesis is very important and is widely used in the electronic and communication system applications. In 1999, El-Ela proposed that additional signal which is a synchronized saw-tooth waveform from the D/A converter is injected into the VCO input of the conventional PLL frequency synthesizer for the high speed operation [1]. 中文 高速数字混合锁相环频率合成器 摘要：传统的锁相环频率合成器需要很长的切换时间,因为其内在的闭环结构。 目前已经研发的一种数字混合锁相环来解决这一问题——在传统的锁相环频率合成器中加入开环结构。 它可以高速运行，但硬件复杂度和功耗是一个严重的问题，因为它的数字查找表（包含压控振荡器的传输特性）在ROM中频繁执行。 本文提出一种新的数字混合锁相环——使用一种简单的数字查找表代替复杂的ROM型数字查找表。 此外，定时同步电路使得环路超调量很小且建立时间短，从而保证了超高速切换速度。 同时,硬件复杂度和功耗比传统的数字混合锁相环（DH-PLL）大约降低28%。 关键词：锁相环（PLL），数值查找表（DLT），频率合成 1简介 高速频率合成是一种非常重要的技术,被广泛地应用在电子和通信系统应用。 在1999年,El-Ela提出在传统锁相环频率合成器压控振荡器的输入端注入额外的信号——从D/A转换器上得到的同步锯齿波——可以使它高速度运行【1】。 第2页/共10页
However, it needs the optimal slope and duration at every frequency synthesis.
To get the high-speed, it is necessary to prepare the precise synchronization of the complicated design.
In 2001, H. G. Ryu proposed a simplified structure of the DDFS (direct digital frequency synthesizer)-driven PLL for the high switching speed [2].
However, there is a problem that the speed of the whole system is limited by PLL.
Y. Fouzar proposed a PLL frequency synthesizer of dual loop configuration using frequency-to-voltage converter (FVC) [3]. It has a fast switching speed by the PD (phase detector), FVC using output signal of VCO and the proposed coarse tuning controller.
However, H/W complexity is increased for the high switching speed.
Also, it shows the fast switching characteristic only when the FVC works well.
Another method is pre-tuning one which is called DH-PLL in this study [4].
It has very high speed switching property, but H/W complexity and power consumption are increased due to digital look-up table (DLT) which is usually implemented by the ROM including the transfer characteristic of VCO(voltage controlled oscillator).
For this reason, this paper proposes a timing synchronization circuit for the rapid frequency synthesis and a very simple DLT replacement digital logic block instead of the complex ROM type DLT for high speed switching and low power consumption. Also, the requisite condition is solved in the proposed method. The fast switching operation at every the frequency synthesis process is verified by the computer circuit simulation.
II. DH-PLL synthesizer
但是，该锯齿波在每一次频率合成
时需要最理想的斜率和持续时间。 要得到高运行速度,事先做好复杂设计的精确同步是必要的。
2001年,H.G.Ryu提出了一种简化结构的直接数字频率合成器(DDFS)驱动的高转换速度锁相环 【2】。
但是,有一个问题,整个系统的速度是受锁相环限制的。
Y.Fouzar提出了一种使用频率—电压转换器(FVC)具有双重回路结构的锁相环频率合成器【3】。
因为鉴相器(PD)， FVC利用了压控振荡器的输出信号和我们提出的粗调控制器，所以它具有快速切换速度。
但是,因为有高速系统转换速度使得H / W的复杂性增加了。
另外，结果表明只有FVC工作状态良好时系统才有较高切换速度。
另一种方法是做预先调整也就是本项研究中的DH-PLL 【4】。
它具有高速切换的特性，但是因为数字查找表(DLT)的原因，H / W复杂度和功耗明显增大了，因为DLT经常被ROM执行，DLT中包含压控振荡器(VCO)的传输特性。
介于以上原因, 为得到较高切换速度和低功耗，本文提出了一种新的快速定时同步频率合成电路，用一个非常简单的DLT替代数字逻辑块，而不用复杂的ROM型(DLT)。
同时,在该方法中所需必要条件也解决了，频率合成过程的高切换速度在计算机电路仿真中已经得到验证了。
2.DH-PLL合成器
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As shown in Fig.1, the open-loop synthesizer is a direct frequency synthesis type that VCO generates the desired output by the FCW (frequency control word) input from the D/A converter. The digital frequency word which is produced from the ROM type DLT (digital look-up table) containing the VCO transfer characteristic goes into D/A converter that generates the DC value corresponding to the desired VCO frequency. 图1中所示的开环频率合成技术是一种直接频率合成方式，在频率控制字（FCW）控制下VCO产生了期望的输出,VCO输入来自于D / A转换器。 该数字频率控制字是由ROM类型的包含压控振荡器传输特性的数字查找表（DLT)产生的，进入D / A转换器,生成与预期的压控振荡器的频率值相对应的直流电压。 Fig. 1. Open-loop frequency synthesizer. 图1 .开环频率合成器。 The DC value is already found by the voltage-frequency characteristics of VCO. This open-loop frequency synthesizer has fast switching speed. However, it has the big problems of stability and sensitivity due to the inherent properties of the open loop structure. Therefore, this synthesizer type is not so attractive that this synthesizer is not widely used. 直流电压值已经根据VCO的电压—频率特性建立了。 该开环频率合成器具有高切换速度。 但是, 由于开环结构的固有特性,该频率合成器在稳定性和灵敏度方面还有比较大的问题。 因此,这种合成器类型缺乏吸引力,该合成器没有广泛应用。 第4页/共10页
Fig. 2. Closed-loop PLL frequency synthesizer. 图 2.闭合回路PLL 频率合成器。 In Fig. 2, FCW (frequency control word) is the division ratio command for frequency synthesis. This structure is very popular and excellent in the aspects of the stability, variety and flexibility. Also, the spurious noise is smaller than other frequency synthesizer. It takes the longer acquisition time to jump into a new frequency so that the switching speed is low. The switching time gets longer as the generation frequency spacing is increased. DH-PLL frequency synthesizer is shown in Fig.3. 在图2中，频率控制字（FCW）为频率合成分频比控制指令。 这种结构在稳定度、多样性和适应性方面是非常流行、优良的。 同时，寄生噪音是比其他的频率合成器要小。 它需要较长的捕获时间来跳变为一个新的频率，因而切换速度低。 如果当前频率与生成频率的间隔增加时，系统切换时间也增加了。 DH-PLL频率合成器如图3所示。 Fig.3.DH-PLL using DLT (digital look-up table). 图3.采用数字查表（DLT）的DH-PLL。 The open-loop structure of the DLT and DAC is combined into the conventional PLL closed-loop structure. In the conventional PLL, the output voltage of LF is fed to the VCO. On the contrary, sum of DAC output voltage and the LF output voltage drives the VCO whenever FCW is changed. Therefore, unlike conventional PLL, DAC outputs the steady state driving voltage at every new FCW change times so that high speed frequency switching may be possible. However, the DH-PLL has a serious problem of the phase change at every new frequency synthesis. DLT开环结构和DAC组合成传统的锁相环闭环结构。 在传统锁相环中,输出的低频电压反馈到压控振荡器。 相反,每当FCW改变，DAC输出电压的总和与低频输出电压一起驱动压控振荡器。 因此,与传统的锁相环不同，每当FCW更新时，该锁相环的DAC能输出电压的稳定的驱动压，所以,高速频率切换就可以实现。 但是,在进行一个新频率合成时，DH-PLL有一个严重的相位变化的问题。 第5页/共10页
锁相环英文文献翻译--高速数字混合锁相环频率合成器
