2.Intel Agilex I/O Features and Usage
UG-20244 | 2024.04.05
2.3.2.1. Release Information
Intel FPGA IP versions match the Intel Quartus Prime Design Suite software versionsuntil v19.1. Starting in Intel Quartus Prime Design Suite software version 19.2, IntelFPGA IP has a new versioning scheme.
The Intel FPGA IP version (X.Y.Z) number can change with each Intel Quartus Primesoftware version. A change in:???
Table 8.
X indicates a major revision of the IP. If you update the Intel Quartus Primesoftware, you must regenerate the IP.
Y indicates the IP includes new features. Regenerate your IP to include these newfeatures.
Z indicates the IP includes minor changes. Regenerate your IP to include thesechanges.
GPIO Intel FPGA IP Release Information
Item
Description
20.0.021.12024.03.29
IP Version
Intel Quartus Prime VersionRelease Date
Related Information
GPIO Intel FPGA IP Release Notes
2.3.2.2. GPIO Intel FPGA IP Quick Start Guide
2.3.2.2.1. Generating the GPIO Intel FPGA IP (Intel Quartus Prime Pro Edition)
Double-click the GPIO Intel FPGA IP in the IP Catalog to launch the parameter editor.The parameter editor allows you to define a custom variation of the IP. The parametereditor generates the IP variation synthesis and optional simulation files, and addsthe .ip file representing the variation to your project automatically.
Follow these steps to locate, instantiate, and customize the IP in the parameter editor:1.2.3.
Create or open an Intel Quartus Prime project (.qpf) to contain the instantiatedIP variation.
In the IP Catalog (Tools ? IP Catalog), locate and double-click the GPIO IntelFPGA IP to customize.
Specify a top-level name for your custom IP variation. Do not include spaces in IPvariation names or paths. The parameter editor saves the IP variation settings in afile named
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2.Intel Agilex I/O Features and UsageUG-20244 | 2024.04.05
Figure 13.GPIO Intel FPGA IP Parameter Editor
4.
Set the parameter values in the parameter editor and view the block diagram forthe component. The Parameterization Messages tab at the bottom displays anyerrors in IP parameters.
Click Generate HDL. The Generation dialog box appears.
Specify output file generation options, and then click Generate. The synthesis andsimulation files generate according to your specifications.
To generate a simulation testbench, click Generate ? Generate TestbenchSystem. Specify testbench generation options, and then click Generate.To generate an HDL instantiation template that you can copy and paste into yourtext editor, click Generate ? Show Instantiation Template.
Click Finish. Click Yes if prompted to add files representing the IP variation toyour project.
5.6.7.8.9.
10.After generating and instantiating your IP variation, make appropriate pin
assignments to connect ports.
2.3.2.2.2. GPIO Intel FPGA IP Parameter Settings
You can set the parameter settings for the GPIO IP in the Intel Quartus Primesoftware. There are three groups of options: General, Buffer, and Registers.
Table 9.
General
Condition—???ValuesInputOutputBidirDefaultOutputDescriptionSpecifies the data direction for theGPIO.ParameterData DirectionData widthUse legacy top-levelport names——1 to 128??OnOff4OffSpecifies the data width.Use the same port names as inStratix? V, Arria? V, and Cyclone? Vdevices.For example, dout becomesdataout_h and dataout_l, and dinbecomes datain_h and datain_l.continued... Send Feedback
FPGA可编程逻辑器件芯片EP3C10U256C7中文规格书
