High-Speed I/O Interface Functional Description
Table2.StratixGX Package Options & I/O Pin Counts(Part 2 of2)Note(1)
Device
672-Pin FineLine BGA
1,020-Pin FineLine BGA
EP1SGX25D455
607EP1SGX25F607EP1SGX40D624EP1SGX40G624
Note to Table2:(1)
The number of I/O pins listed for each package includes dedicated clock pins and
dedicated fast I/O pins. However, these numbers do not include high-speed or clock reference pins for high-speed I/O standards.
Table3.StratixGX FineLine BGA Package Sizes
Dimension
672 Pin
1,020 Pin
Pitch (mm)1.001.00Area (mm2)
7291,089Length×width (mm×mm)
27×27
33×33
Table4.StratixGX Device Speed Grades
Device
672-Pin FineLine BGA
1,020-pin FineLine BGA
EP1SGX10-5, -6, -7EP1SGX25-5, -6, -7
-5, -6, -7EP1SGX40
-5, -6, -7
The StratixGX device family supports high-speed serial transceiver blocks with CDR circuitry as well as source-synchronous interfaces. The channels on the right side of the device use an embedded circuit
dedicated for receiving and transmitting high-speed serial data streams to and from the system board. These channels are clustered in a
four-channel serial transceiver building block and deliver high-speed bidirectional point-to-point data transmissions to provide up to
3.1875Gbps of full-duplex data transmission per channel. The channels on the left side of the device support source-synchronous data transfers at up to 1 Gbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure1 shows the StratixGX I/O blocks. The differential source-synchronous serial interface is described in
“Principles of SERDES Operation” on page47 and the high-speed serial interface is described in “Transceiver Blocks” on page8.
FPGA Functional Description
Figure1.StratixGX I/O Blocks
DQST9PLL7Note(1)
DQST59PLL510DQST4PLL11DQST3DQST2Bank 4DQST8DQST7Bank 3DQST6DQST1DQST0VREF1B3VREF2B3VREF3B3VREF4B3VREF5B3VREF1B4VREF2B4VREF3B4VREF4B4VREF5B4VREF1B2VREF2B2VREF3B2VREF4B2I/O Bank 13 (5)LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Blockand Regular I/O Pins (3)Bank 2(4)I/O Banks 3, 4, 9 & 10 Support All Single-Ended I/O Standards (2)I/O Bank 14 (5)PLL1PLL2VREF1B1VREF2B1VREF3B1VREF4B1I/O Banks 1 and 2 Support AllSingle-Ended I/O Standards Except Differential HSTL Output Clocks, Differential SSTL-2 Output Clocks, HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1×/2× 1.5-V PCML (5)I/O Bank 17 (5)Bank 1(4)LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Blockand Regular I/O Pins (3)I/O Banks 7, 8, 11 & 12 Support All Single-Ended I/O Standards (2)I/O Bank 16 (5)I/O Bank 15 (5)Bank 811DQSB6DQSB512PLL12DQSB4DQSB3Bank 7VREF5B7VREF4B7VREF3B7VREF2B7VREF1B7VREF5B8VREF4B8VREF3B8VREF2B8VREF1B8PLL8DQSB9DQSB8DQSB7PLL6DQSB2DQSB1DQSB0Notes to Figure1:(1)(2)(3)(4)(5)
Figure1 is a top view of the StratixGX silicon die.
Banks 9 through 12 are enhanced PLL external clock output banks.
If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the I/O standards except HSTL class I and II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1×/2×.
For guidelines for placing single-ended I/O pads next to differential I/O pads, see the Selectable I/O Standards inStratix & StratixGX Devices chapter in the Stratix Device Handbook, Volume 2.
These I/O banks in StratixGX devices also support the LVDS, LVPECL, and 3.3-V PCML I/O standards on reference clocks and receiver input pins (AC coupled).
FPGA Functional Description
StratixGX devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks.
StratixGX FPGA Family
Each StratixGX transceiver channel consists of a transmitter and receiver. The transmitter contains the following:
■■■■■■
Transmitter PLL
Transmitter phase compensation FIFO bufferByte serializer8B/10B encoder
Serializer (parallel to serial converter)Transmitter output buffer
The receiver contains the following:
■■■■■■■
Input buffer
Clock recovery unit (CRU)Deserializer
Pattern detector and word alignerRate matcher and channel aligner8B/10B decoder
Receiver logic array interface
Designers can set all the StratixGX transceiver functions through the QuartusII software. Designers can set programmable pre-emphasis, programmable equalizer, and programmable VOD dynamically as well. Each StratixGX transceiver channel is also capable of BIST generation and verification in addition to various loopback modes. Figure4 shows the block diagram for the StratixGX transceiver channel.
StratixGX transceivers provide physical coding sublayer (PCS) and physical media attachment (PMA) implementation for protocols such as 10-gigabit XAUI and GigE. The PCS portion of the transceiver consists of the logic array interface, 8B/10B encoder/decoder, pattern detector, wordaligner, rate matcher, channel aligner, and the BIST and pseudo-randombinary sequence pattern generator/verifier. The PMA portion of thetransceiver consists of the serializer/deserializer, the CRU, and the I/Obuffers.
StratixGX FPGA Family
Transmitter Path
This section describes the data path through the StratixGX transmitter (see Figure4). Data travels through the StratixGX transmitter via the following modules:
■■■■■■
Transmitter PLL
Transmitter phase compensation FIFO bufferByte serializer8B/10B encoder
Serializer (parallel to serial converter)Transmitter output buffer
Transmitter PLL
Each transceiver block has one transmitter PLL, which receives the reference clock and generates the following signals:
■■■
High-speed serial clock used by the serializerSlow-speed reference clock used by the receiver
Slow-speed clock used by the logic array (divisible by two fordouble-width mode)
The INCLK clock is the input into the transmitter PLL. There is one INCLK clock per transceiver block. This clock can be fed by either the REFCLKB pin, PLD routing, or the inter-transceiver routing line. See the section “StratixGX Clocking” on page36 for more information about the inter-transceiver lines.
The transmitter PLL in each transceiver block clocks the circuits in the transmit path. The transmitter PLL is also used to train the receiver PLL. If no transmit channels are used in the transceiver block, the transmitter PLL can be turned off. Figure5 is a block diagram of the transmitter PLL.Figure5.Transmitter PLL Block Diagram
÷mNote(1)
ClockDriverHigh Speed ClockLow Speed ClockUpInter Quad Routing (IQ1)Inter Quad Routing (IQ2)Global Clks, IO Bus, Gen RoutingINCLKPFDDownCharge Pump +Loop FilterVCODedicatedLocalREFCLKB÷2Note to Figure5:(1)
The divider in the PLL divides by 4, 8, 10, 16, or 20.
Transceiver Blocks
XAUI Mode
The transmit state machine translates the XAUI XGMII code group to the XAUI PCS code group. Table8 shows the code conversion.Table8.Code ConversionXGMII TXC
01111111
XGMII TXD
00 through FF07079CFBFDFE
PCS Code-Group
Dxx.y
K28.0 or K28.3 or K28.5K28.5K28.4K27.7K29.7K30.7
Description
Normal dataIdle in ||I||Idle in ||T||SequenceStartTerminateError
See IEEE 802.3 See IEEE 802.3 Reserved Code GroupsReserved Code Reserved Code GroupsGroupsOther value
K30.7
Invalid XGMII character
1
FPGA可编程逻辑器件芯片EP1SGX25FF1020中文规格书 - 图文
