3.Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2021.02.05
resultb = bx * by
Figure 16.
Two 18 × 18 or 18 × 19 Independent Multiplier per Variable Precision DSPBlock
In this figure, the variables are defined as follows:??
n = 19 and m = 37 for 18 × 19 signed operandsn = 18 and m = 36 for 18 × 18 unsigned operands
Variable-Precision DSP Blocknay [(n-1)..0]
Multipliermx18*2nd Pipeline Register*1st Pipeline RegisterOutput Register BankInput Register Bankax [17..0]
resulta[(m-1)..0]Multipliernby [(n-1)..0]
18bx [17..0]
xmresultb[(m-1)..0]*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
3.1.1.2. 27 × 27 Independent Multiplier
The 27 x 27 independent multiplier mode uses the equation of resulta = ay * ax.
Figure 17.
One 27 × 27 Independent Multiplier Mode per Variable Precision DSP Blockfor Intel Agilex Devices
In this mode, the resulta can be up to 64 bits when combined with a chainout adder or accumulator.
Variable-Precision DSP BlockMultiplier*2nd Pipeline Registeray[26..0]27*1st Pipeline RegisterOutput Register BankInput Register Bank2754xresulta[53..0]ax[26..0]*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.Send Feedback
3.Intel Agilex Variable Precision DSP Blocks Operational ModesUG-20213 | 2021.02.05
3.1.2. 8 x 8 (unsigned) or 9 x 9 (signed) Sum of 4 Mode
The 8 x 8 (unsigned) or 9 x 9 sum of 4 mode uses the following equations:resulta = (ax * ay)+(bx * by)+(cx * cy)+(dx * dy)
Figure 18.
9 × 9 Sum of 4
In this figure, the variables are defined as follows:??
n = 8 and m = 8 for 8 x 8 unsigned operandsn = 9 and m = 9 for 9 x 9 signed operands
Variable-Precision DSP Blockay [(n-1)..0]9Multiplierx*2nd Pipeline Register*1st Pipeline RegisterInput Register Bankax [(n-1)..0]9Adder+Multiplierby [(n-1)..0]9x9bx [(n-1)..0]Adder+Output Register BankMultiplier9cy [(n-1)..0]xcx [(n-1)..0]9Adderresulta[(63..0]+Multiplierdy [(n-1)..0]9xdx [(n-1)..0]9*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
3.1.3. Multiplier Adder Sum Mode
The multiplier adder sum mode uses the equations:??
resulta = (bx * by) + (ax * ay) to calculate the sum of the two 18 x 19multiplications.
resulta = (bx * by) - (ax * ay) to calculate the difference of the two 18 x 19multiplications.
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3.Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2021.02.05
Figure 19.
One Sum of Two 18 x 18 or 18 × 19 Multipliers with One Variable PrecisionDSP Block for Intel Agilex Devices
In this figure, the variable is defined as follows:??
n = 19 for 18 × 19 signed operandsn = 18 for 18 × 18 unsigned operands
Variable-Precision DSP BlockSUB
nMultiplieray[(n-1)..0]x18*2nd Pipeline Register*1st Pipeline RegisterInput Register BankOutput Register Bankax17..0]38+/-resulta[37..0]
nMultiplierAdderxby[(n-1)..0]18bx[17..0]*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
Set the SUB dynamic control signal to high to calculate the difference of the two18 × 19 multiplications.
3.1.4. Independent Complex Multiplier
The Intel Agilex devices support the 18 × 19 complex multiplier mode using two fixed-point arithmetic multiplier adder sum mode.
Figure 20.
Sample of Complex Multiplication Equation
The imaginary part [(a × d) + (b × c)] is implemented in the first variable-precisionDSP block, while the real part [(a × c) - (b × d)] is implemented in the secondvariable-precision DSP block.
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