Chapter 1:Configuration Overview
Table 1-12:Signals Relating to Synchronization
TypeStatus
Access
Description
Signal NameDALIGN
Only available through the SelectMAP interface Indicates whether the device is during an ABORT sequence. (See “Configuration synchronized.Abort Sequence Description,” page58.)
Internal signal. Accessed only through the Virtex-5 Status register.(1)
IWIDTHStatusIndicates the detected bus width:00011011
====x1x8x16x32
If ICAP is enabled, this signal reflects the ICAP width after configuration is done.
Notes:
1.Information on the Virtex-5 status register is available in Table6-9. Information on accessing the device status register via JTAG isavailable in Table7-5. Information on accessing the device status register via SelectMAP is available in Table7-1.
Check Device ID (Step 5)
Steps
1DevicePower-Up2ClearConfigurationMemory3Sample ModePins4Synchronization5Device IDCheck6LoadConfigurationData7CRC Check8StartupSequenceStartBitstreamLoadingFinishUG191_c1_07_050406
Figure 1-8:Check Device ID (Step 5)
After the device is synchronized, a device ID check must pass before the configuration data frames can be loaded. This prevents a configuration with a bitstream that is formatted for a different device. For example, the device ID check should prevent an XC5VLX30 from being configured with an XC5VLX50 bitstream.
If an ID error occurs during configuration, the device attempts to do a fallback reconfiguration (see “Fallback MultiBoot,” page153).
The device ID check is built into the bitstream, making this step transparent to most
designers. Table1-13 shows the Virtex-5 device ID codes, and Table1-14 shows the signals relating to the device ID check. The device ID check is performed through commands in the bitstream to the configuration logic, not through the JTAG IDCODE register in this case.
The Virtex-5 JTAG ID Code register has the following format:
vvvv:fffffff:aaaaaaaaa:cccccccccc11
where
v=revision
f=7-bit family code (0010101=XC5VLXT, 0010100=XC5VLX, 0010111=XC5VSXT,and0011001=XC5VFXT)a=number of array rows plus array columnsc=company code
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Configuration Sequence
Table 1-13:Virtex-5 Device ID Codes
ID Code (Hex)
Device
Revision CodeSee Note 1See Note 1See Note 1See Note 1See Note 1See Note 1See Note 1See Note 1See Note 1See Note 1See Note 1
See Note1See Note1See Note 1
See Note1See Note 1See Note 1See Note 1See Note 1See Note 1See Note 1See Note 1See Note 1See Note 1See Note 1See Note 1
Family, Array, and Company
Code
286E093289609328AE09328D609328EC093290C093295C0932A560932A6E0932A960932AAE0932AD60932AEC0932B0C0932B5C0932E720932E9A0932ECE0932F3E093327609332C609332D8093330009333340934502093453E093
XC5VLX30XC5VLX50XC5VLX85XC5VLX110XC5VLX155XC5VLX220XC5VLX330XC5VLX20TXC5VLX30TXC5VLX50TXC5VLX85T
CX5VLX110TCX5VLX155T
XC5VLX220T
CX5VLX330T
XC5VSX35TXC5VSX50TXC5VSX95TXC5VSX240TXC5VFX30TXC5VFX70TXC5VFX100TXC5VFX130TXC5VFX200TXC5VTX150TXC5VTX240T
Notes:
1.The value of the Version code can be 0x0 to 0xF.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Chapter 1:Configuration Overview
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
???
Sending a bitstream to the data pin follows the same bit-swapping rule as inSelectMAP mode. See “Parallel Bus Bit Order.”
If Flash programming is not required, FCS_B, FOE_B, and FWE_B can be tied off; thatis, DONE is connected to FCS_B, FOE_B is tied Low, and FWE_B is tied High.The CCLK outputs are not used to connect to Flash but are used to sample Flash readdata during configuration. All timings are referenced to CCLK. The CCLK pin mustnot be driven or tied High or Low.
The RS[1:0] pins are not connected as shown in Figure2-22. These output pins areonly required for MultiBoot configuration. See Chapter8, “Reconfiguration andMultiBoot.”
HSWAPEN must be connected to either disable or enable the pull-up resistors.If HSWAPEN is left unconnected or tied High, a pull-up resistor is required forFCS_B.
If HSWAPEN is tied Low, the FCB_B, FOE_B, FWE_B, and the address pins haveinternal weak pull-up resistors during configuration. After configuration, FCS_B canbe either controlled by I/O in user mode or by enabling a weak pull-up resistorthrough constraints.
To enable the active driver on DONE, the DriveDONE option in BitGen must beenabled.
“MultiBoot Bitstream Spacing,” page155 provides information on when DCI or DCMlock wait is turned on.
For daisy chaining FPGAs in BPI mode, see Figure2-12, page52.
The BPI Flash vendor data sheet should be referred to for details on the specific Flashsignal connectivity. To prevent address misalignment, close attention should be paidto the Flash family address LSB for the byte/word mode used. Not all Flash familiesuse the A0 as the address LSB.
?
???
????
Table2-9 defines the BPI configuration interface pins.
If the FPGA is subject to reprogramming or fallback during configuration from the BPI flash, then the INIT pin can be connected to the BPI reset to set the BPI into a known state.
Table 2-9:
Virtex-5 Device BPI Configuration Interface Pins
Type Input
Dedicated or Dual-Purpose
010 = BPI-Up mode011 = BPI-Down mode
HSWAPEN
Input
Dedicated
Controls I/O (except Bank 0 dedicated I/Os) pull-up resistors during configuration. This pin has a built-in weak pull-up resistor.0 = Pull-up during configuration1 = 3-state during configuration
DONE
Bidirectional, Dedicated Active-High signal indicating configuration is complete: Open-Drain, 0 = FPGA not configured or Active
1 = FPGA configured
Description
Pin Name M[2:0]
Dedicated The Mode pins determine the BPI mode:
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
FPGA可编程逻辑器件芯片XC2V80-5FF1517C中文规格书 - 图文
