Spartan-3 FPGA Family: Functional Description
Table 13:Block RAM Port Signals (Cont’d)
Signal DescriptionData Output Bus
Port A Port B Signal NameSignal Name
DOA
DOB
DirectionOutput
Function
Basic data access occurs whenever WE is inactive. The DO outputs mirror the data stored in the addressed memory location.
Data access with WE asserted is also possible if one of the following two attributes is chosen: WRITE_FIRST and READ_FIRST. WRITE_FIRST simultaneously presents the new input data on the DO output port and writes the data to the address RAM location. READ_FIRST presents the previously stored RAM data on the DO output port while writing new data to RAM.
A third attribute, NO_CHANGE, latches the DO outputs upon the assertion of WE.
It is possible to configure a port’s total data path width (w) to be 1, 2, 4, 9, 18, or 36 bits. This selection applies to both the DI and DO paths. See the DI signal description.
Parity inputs represent additional bits included in the data input path to support error detection. The number of parity bits \(same as for the DO bus) depends on a port’s total data path width (w). See Table14.
When asserted together with EN, this input enables the writing of data to the RAM. In this case, the data access attributes WRITE_FIRST, READ_FIRST or NO_CHANGE determines if and how data is updated on the DO outputs. See the DO signal description.
When WE is inactive with EN asserted, read operations are still possible. In this case, a transparent latch passes data from the addressed memory location to the DO outputs.
When asserted, this input enables the CLK signal to synchronize Block RAM functions as follows: the writing of data to the DI inputs (when WE is also asserted), the updating of data at the DO outputs as well as the setting/resetting of the DO output latches.
When de-asserted, the above functions are disabled.
When asserted, this pin forces the DO output latch to the value that the SRVAL attribute is set to. A Set/Reset operation on one port has no effect on the other ports functioning, nor does it disturb the memory’s data contents. It is synchronized to the CLK signal.
This input accepts the clock signal to which read and write operations are synchronized. All associated port inputs are required to meet setup times with respect to the clock signal’s active edge. The data output bus responds after a clock-to-out delay referenced to the clock signal’s active edge.
Parity Data Output(s)
DOPADOPBOutput
Write EnableWEAWEBInput
Clock EnableENAENBInput
Set/ResetSSRASSRBInput
ClockCLKACLKBInput
Port Aspect Ratios
On a given port, it is possible to select a number of different possible widths (w – p) for the DI/DO buses as shown in
Table14. These two buses always have the same width. This data bus width selection is independent for each port. If the data bus width of Port A differs from that of Port B, the Block RAM automatically performs a bus-matching function. When data are written to a port with a narrow bus, then read from a port with a wide bus, the latter port will effectively combine “narrow” words to form “wide” words. Similarly, when data are written into a port with a wide bus, then read from a port with a narrow bus, the latter port will divide “wide” words to form “narrow” words. When the data bus width is eight bits or greater, extra parity bits become available. The width of the total data path (w) is the sum of the DI/DO bus width and any parity bits (p).
The width selection made for the DI/DO bus determines the number of address lines according to the relationship expressed below:
r = 14 – [log(w–p)/log(2)]
Equation1
In turn, the number of address lines delimits the total number (n) of addressable locations or depth according to the following equation:
n = 2r
DS099 (v3.1) June 27, 2013Product Specification
Equation2
Spartan-3 FPGA Family: Functional Description
The product of w and n yields the total block RAM capacity. Equation1 and Equation2 show that as the data bus width increases, the number of address lines along with the number of addressable memory locations decreases. Using the permissible DI/DO bus widths as inputs to these equations provides the bus width and memory capacity measures shown in Table14.
Table 14:Port Aspect Ratios for Port A or B
DI/DO Bus Width(w – p Bits)
12481632
DIP/DOP Bus Width (p Bits)
000124
Total Data Path Width (w Bits)
12491836
ADDR Bus Width
(r Bits)
14131211109
No. of Addressable Block RAM Locations (n)Capacity (Bits)
16,3848,1924,0962,0481,024512
16,38416,38416,38418,43218,43218,432
Block RAM Data Operations
Writing data to and accessing data from the block RAM are synchronous operations that take place independently on each
of the two ports.
The waveforms for the write operation are shown in the top half of the Figure15, Figure16, and Figure17. When the WE and EN signals enable the active edge of CLK, data at the DI input bus is written to the block RAM location addressed by the ADDR lines.
There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access always occurs when the WE input is inactive. Under this condition, data stored in the memory location addressed by the ADDR lines passes through a transparent output latch to the DO outputs. The timing for basic data access is shown in the portions of Figure15, Figure16, and Figure17 during which WE is Low.
X-Ref Target - Figure 15CLKWEDIADDRDOXXXX11112222XXXXaabbccdd0000MEM(aa)11112222MEM(dd)ENDISABLEDREADWRITEMEM(bb)=1111WRITEMEM(cc)=2222READDS099-2_14_091410Figure 15:Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Data can also be accessed on the DO outputs when asserting the WE input. This is accomplished using two different attributes:
Choosing the WRITE_FIRST attribute, data is written to the addressed memory location on an enabled active CLK edge and is also passed to the DO outputs. WRITE_FIRST timing is shown in the portion of Figure15 during which WE is High.Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that location is overwritten with new data from the DI inputs on an enabled active CLK edge. READ_FIRST timing is shown in the portion of Figure16 during which WE is High.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
CLKWEDIADDRDOENDISABLEDREADWRITEMEM(bb)=1111WRITEMEM(cc)=2222READDS099-2_15_030403XXXX11112222XXXXaabbccdd0000MEM(aa)old MEM(bb)old MEM(cc)MEM(dd)Figure 16:Waveforms of Block RAM Data Operations with READ_FIRST Selected
Choosing a third attribute called NO_CHANGE puts the DO outputs in a latched state when asserting WE. Under this condition, the DO outputs will retain the data driven just before WE was asserted. NO_CHANGE timing is shown in the portion of Figure17 during which WE is High.
X-Ref Target - Figure 17CLKWEDIADDRDOENDISABLEDREADWRITEMEM(bb)=1111WRITEMEM(cc)=2222READDS099-2_16_030403XXXX11112222XXXXaabbccdd0000MEM(aa)MEM(dd)Figure 17:Waveforms of Block RAM Data Operations with NO_CHANGE Selected
Dedicated Multipliers
All Spartan-3 devices provide embedded multipliers that accept two 18-bit words as inputs to produce a 36-bit product. This section provides an introduction to multipliers. For further details, refer to the chapter entitled “Using Embedded Multipliers” in UG331.
The input buses to the multiplier accept data in two’s-complement form (either 18-bit signed or 17-bit unsigned). One such multiplier is matched to each block RAM on the die. The close physical proximity of the two ensures efficient data handling. Cascading multipliers permits multiplicands more than three in number as well as wider than 18-bits. The multiplier is placed in a design using one of two primitives: an asynchronous version called MULT18X18 and a version with a register called MULT18X18S, as shown in Figure18. The signals for these primitives are defined in Table15.
The CORE Generator system produces multipliers based on these primitives that can be configured to suit a wide range of requirements.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2V80-5FF1152C中文规格书 - 图文
