NRF24l01使用手册函数介绍

uchar status,byte_ctr;

CSN = 0; // Set CSN low, init SPI tranaction

status = SPI_RW(reg); // Select register to write to and read status byte Uart_Delay(10);

for(byte_ctr=0; byte_ctr

CSN = 1; // Set CSN high again

return(status); // return nRF24L01 status byte }

发射缓冲区访问函数：主要用来把数组里的数放到发射 FIFO 缓冲区中。基本思路就通过WRITE_REG 命令把数据存到发射 FIFO（ WR_TX_PLOAD）中去。

4.1.6 void RX_Mode(void)

设定 24L01 为接收方式，配置过程详见 3.2 Rx 模式初始化过程。 void RX_Mode(void) {

CE=0;

SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0 SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0 SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40 SPI_RW_Reg(WRITE_REG + RX_PW_P0, TX_PLOAD_WIDTH); SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07);

SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:RX. RX_DR enabled..

CE = 1; // Set CE pin high to enable RX device

// This device is now ready to receive one packet of 16 bytes payload from a TX device sending to address

// '3443101001', with auto acknowledgment, retransmit count of 10, RF channel 40 and datarate = 2Mbps. }

4.1.7 void TX_Mode(void)

设定 24L01 为发送方式，配置过程详见 3.1 Tx 模式初始化过程。

void TX_Mode(void) { CE=0;

SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); SPI_Write_Buf(WR_TX_PLOAD, tx_buf, TX_PLOAD_WIDTH); // Writes data to TX payload SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0 SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0

SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x1a); // 500us + 86us, 10 retrans... SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40

SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR

SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:TX. MAX_RT & TX_DS enabled.. CE=1; }

4.2NRF24L01相关命令的宏定义

nRF24L01 的基本思路就是通过固定的时序与命令，控制芯片进行发射与接收。控制命令如FIG..4.2.1 所示。

前面提到的函数也要与这些命令配合使用,比如

SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01);

SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); 相关命令的宏定义如下：

#define READ_REG 0x00 // Define read command to register #define WRITE_REG 0x20 // Define write command to register

#define RD_RX_PLOAD 0x61 // Define RX payload register address #define WR_TX_PLOAD 0xA0 // Define TX payload register address #define FLUSH_TX 0xE1 // Define flush TX register command #define FLUSH_RX 0xE2 // Define flush RX register command

#define REUSE_TX_PL 0xE3 // Define reuse TX payload register command #define NOP 0xFF // Define No Operation, might be used to read statusregister

4.3NRF24l01相关寄存器地址宏定义

#define CONFIG 0x00 // 'Config' register address

#define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address #define EN_RXADDR 0x02 // 'Enabled RX addresses' register address #define SETUP_AW 0x03 // 'Setup address width' register address #define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address #define RF_CH 0x05 // 'RF channel' register address #define RF_SETUP 0x06 // 'RF setup' register address #define STATUS 0x07 // 'Status' register address

#define OBSERVE_TX 0x08 // 'Observe TX' register address #define CD 0x09 // 'Carrier Detect' register address

#define RX_ADDR_P0 0x0A // 'RX address pipe0' register address #define RX_ADDR_P1 0x0B // 'RX address pipe1' register address #define RX_ADDR_P2 0x0C // 'RX address pipe2' register address #define RX_ADDR_P3 0x0D // 'RX address pipe3' register address #define RX_ADDR_P4 0x0E // 'RX address pipe4' register address #define RX_ADDR_P5 0x0F // 'RX address pipe5' register address #define TX_ADDR 0x10 // 'TX address' register address

#define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address #define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address #define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address #define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address #define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address #define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address #define FIFO_STATUS 0x17 // 'FIFO Status Register' register address